scholarly journals HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems

2021 ◽  
Vol 20 (5s) ◽  
pp. 1-23
Author(s):  
Mario Günzel ◽  
Christian Hakert ◽  
Kuan-Hsun Chen ◽  
Jian-Jia Chen
Keyword(s):  
Energy Consumption ◽  
Real Time ◽  
Shared Memory ◽  
Computing System ◽  
Dynamic Power Management ◽  
Real Time System ◽  
Extensive Evaluation ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memory Architectures

Dynamic power management (DPM) reduces the power consumption of a computing system when it idles, by switching the system into a low power state for hibernation. When all processors in the system share the same component, e.g., a shared memory, powering off this component during hibernation is only possible when all processors idle at the same time. For a real-time system, the schedulability property has to be guaranteed on every processor, especially if idle intervals are considered to be actively introduced. In this work, we consider real-time systems with hybrid shared-memory architectures, which consist of shared volatile memory (VM) and non-volatile memory (NVM). Energy-efficient execution is achieved by applying DPM to turn off all memories during the hibernation mode. Towards this, we first explore the hybrid memory architectures and suggest a task model, which features configurable hibernation overheads. We propose a multi-processor procrastination algorithm (HEART), based on partitioned earliest-deadline-first (pEDF) scheduling. Our algorithm facilitates reducing the energy consumption by actively enlarging the hibernation time. It enforces all processors to idle simultaneously without violating the schedulability condition, such that the system can enter the hibernation state, where shared memories are turned off. Throughout extensive evaluation of HEART, we demonstrate (1) the increase in potential hibernation time, respectively the decrease in energy consumption, and (2) that our algorithm is not only more general but also has better performance than the state of the art with respect to energy efficiency in most cases.

Ordered arrays of a defect-modified ferroelectric polymer for non-volatile memory with minimized energy consumption

Nanoscale ◽  
2014 ◽  
Vol 6 (22) ◽  
pp. 13945-13951 ◽  
Author(s):  
Xiang-Zhong Chen ◽  
Xin Chen ◽  
Xu Guo ◽  
Yu-Shuang Cui ◽  
Qun-Dong Shen ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Ordered Arrays ◽  
Ferroelectric Polymer ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals Performance analysis comparison between non mixed-criticality and mixed-criticality system in microcontroller

2019 ◽  
Vol 15 (2) ◽  
pp. 678
Author(s):  
Siti Nurhafizza Maidin ◽  
Noor Azurati Ahmad ◽  
Kamilia Kamardin ◽  
Shamsul Sahibuddin ◽  
Syahrizal Fadhlie Sabri
Keyword(s):  
Embedded System ◽  
Real Time ◽  
Dynamic Power Management ◽  
Task Execution ◽  
Real Time System ◽  
Real Time Scheduling ◽  
Time Scheduling ◽  
Save Energy ◽  
Main Component ◽  
Mixed Criticality

<span>Nowadays, implementation of real-time embedded system or safety-critical in a real-time system is significant within emerging technologies because the system involves many aspects such as safety and task execution without missing deadlines. The main cause of implementation is to avoid catastrophic loss. Besides that, effectuation of the mixed-criticality system in embedded system making system more complex for task execution. For an embedded system, the main component involves real-time scheduling. The implementation of DPM method in real-time scheduling is well known, but in the mixed-criticality system, DPM method is still lacking. In order to cater this problem, Dynamic Power management (DPM) method is deployed onto the microcontroller of the mixed-criticality system to save energy when executing tasks in order to have better performance in the system. The usage of the DPM method in mixed-criticality of microcontroller resulting decrease of 0.82% in LED output voltage value meanwhile, for the LCD output, the voltage value decreased by 1.37% in the home alarm system. Thus, the energy-saving in the microcontroller of the mixed-criticality system using the DPM method is defined.</span>

scholarly journals Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures

PLoS ONE ◽  
2021 ◽  
Vol 16 (9) ◽  
pp. e0257047
Author(s):  
Adrián Lamela ◽  
Óscar G. Ossorio ◽  
Guillermo Vinuesa ◽  
Benjamín Sahelices
Keyword(s):  
Markov Model ◽  
Hidden Markov Model ◽  
Hidden Markov ◽  
Multicore Processors ◽  
Memory Access ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memory Accesses ◽  
Access Patterns ◽  
Memory Architectures

Non-volatile memory technology is now available in commodity hardware. This technology can be used as a backup memory for an external dram cache memory without needing to modify the software. However, the higher read and write latencies of non-volatile memory may exacerbate the memory wall problem. In this work we present a novel off-chip prefetch technique based on a Hidden Markov Model that specifically deals with the latency problem caused by complexity of off-chip memory access patterns. Firstly, we present a thorough analysis of off-chip memory access patterns to identify its complexity in multicore processors. Based on this study, we propose a prefetching module located in the llc which uses two small tables, and where the computational complexity of which is linear with the number of computing threads. Our Markov-based technique is able to keep track and make clustering of several simultaneous groups of memory accesses coming from multiple simultaneous threads in a multicore processor. It can quickly identify complex address groups and trigger prefetch with very high accuracy. Our simulations show an improvement of up to 76% in the hit ratio of an off-chip dram cache for multicore architecture over the conventional prefetch technique (g/dc). Also, the overhead of prefetch requests (failed prefetches) is reduced by 48% in single core simulations and by 83% in multicore simulations.

Booting Time Minimization for Real-Time Embedded Systems with Non-Volatile Memory

2014 ◽  
Vol 63 (4) ◽  
pp. 847-859 ◽  
Author(s):  
Che-Wei Chang ◽  
Chuan-Yue Yang ◽  
Yuan-Hao Chang ◽  
Tei-Wei Kuo
Keyword(s):  
Embedded Systems ◽  
Real Time ◽  
Non Volatile Memory ◽  
Time Minimization ◽  
Volatile Memory

Providing Security of Vital Data for Conventional Microcontroller Applications

2015 ◽  
Vol 789-790 ◽  
pp. 1059-1066
Author(s):  
Bayram Akdemir ◽  
Hasan Üzülmez
Keyword(s):  
Real Time ◽  
Power Loss ◽  
Gray Code ◽  
The Other ◽  
Reading Problem ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High Flexibility ◽  
Almost All

Microcontrollers are widely used in industrial world, and almost all kind of devices were based on microcontroller to achieve high flexibility and abilities. All microcontrollers have nonvolatile and volatile memories to execute the software. During the running, microcontroller calculates many variables and records them to any non-volatile memory to use later. After re-energizing, microcontroller takes the data calculated before the power off and executes the program. In case of any electrical writing error or any power loss during the writing procedure, un-written memory blocks or any un-written data leads to malfunctions. Proposed method uses a gray code based signed two memory blocks to secure the memory reserved for data. Microcontroller uses these memory blocks in alternately. Even if microcontroller has no any real-time ability, gray code provides a guarantee which block is written in last. For every re-starting microcontroller dos not lose the data. In case of any reading problem during the starting, microcontroller has two chances to decide the action. One is to start with default values and the other is to start with the previous data. This study is tested at elevator applications not to lose position and vital values.

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