Direct wafer bonding (DWB) is an operation of ultra-fine alignment, joining and thermal bonding of two silicon wafers. The first silicon wafer “handle” substrate is a Czochralski (<CZ>) substrate with N+ arsenic dopant with very low bulk resistivity, whereas second wafer “device” is a float-zone (<FZ>) having extremely high resistivity N-phosphorus dopant. Prior to the joining step, silicon wafers are chemically cleaned in order to minimize surface contamination. The wafer surface is “hydrophobic” which is achieved using an insitu oxide etching process. The surface quality is also characterized in terms of sub-micron light point defects (LPD’s) counts and haze concentration using a laser beam scanning system. After chemical clean, none of the LPD’s counts is greater than 1.0 μ size. The joining step is performed in a Class 100 or better environment by employing a commercial joiner. Then, thermal bonding operation is carried out by employing an extended stream oxidation cycle at elevated temperatures. Typical failure modes of DWB are misalignment errors and “voided” or “disbonded” regions. The area of “voided” regions for each bonded pair is determined by employing a scanning acoustic microscope. Detailed product throughtput and yield data are presented in this paper. A spreading resistivity profile (SRP) system is employed for accurate measurement of doping carrier concentration as a function of the depth. The superior uniformity for capacitance-voltage characteristics of a Si-Si bonded wafer versus an inverse epitaxial silicon wafer substrate is shown in terms of the device performance. The applications of silicon-direct wafer bonded substrates provide a quantum jump in the device electrical performance of PIN diodes.
Reduction of Dark Current in CMOS Image Sensor Pixels Using Hydrocarbon-Molecular-Ion-Implanted Double Epitaxial Si Wafers