High Performance Photoresist Planarization Process by CMP with Resin Abrasive for Trench-First Cu/Low-k Dual Damascene Process

Journal of The Electrochemical Society ◽

10.1149/1.3122883 ◽

2009 ◽

Vol 156 (7) ◽

pp. H548 ◽

Author(s):

Yukiteru Matsui ◽

Satoko Seta ◽

Masako Kinoshita ◽

Yoshikuni Tateyama ◽

Atsushi Shigeta ◽

...

Keyword(s):

High Performance ◽

Dual Damascene ◽

Damascene Process ◽

Planarization Process ◽

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Aqueous Based Single Wafer Cu/Low-k Cleaning Process Characterization and Integration into Dual Damascene Process Flow

Solid State Phenomena - Ultra Clean Processing of Silicon Surfaces VII ◽

10.4028/3-908451-06-x.353 ◽

2005 ◽

pp. 353-356

Author(s):

Jian She Tang ◽

Brian J. Brown ◽

Steven Verhaverbeke ◽

Han Wen Chen ◽

Jim Papanu ◽

...

Keyword(s):

Cleaning Process ◽

Process Flow ◽

Dual Damascene ◽

Damascene Process ◽

Process Characterization ◽

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Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) ◽

10.1109/iitc.2003.1219697 ◽

2004 ◽

Author(s):

A. Kajita ◽

T. Usui ◽

M. Yamada ◽

E. Ogawa ◽

T. Katata ◽

...

Keyword(s):

High Performance ◽

Dual Damascene ◽

Interconnect Technology ◽

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Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) ◽

10.1109/iitc.2004.1345683 ◽

2004 ◽

Author(s):

K.-W. Lee ◽

H.J. Shin ◽

J.W. Hwang ◽

S.W. Nam ◽

Y.J. Moon ◽

...

Keyword(s):

Process Integration ◽

Technology Node ◽

Dual Damascene ◽

Damascene Process ◽

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Effective Defect Control in TiN Metal Hard Mask Cu/Low-k Dual Damascene Process

ECS Transactions ◽

10.1149/05806.0143ecst ◽

2013 ◽

Vol 58 (6) ◽

pp. 143-150 ◽

Author(s):

A. Kabansky ◽

S. S. H. Tan ◽

E. A. Hudson ◽

G. Delgadino ◽

L. Gancs ◽

...

Keyword(s):

Hard Mask ◽

Dual Damascene ◽

Damascene Process ◽

Defect Control ◽

Tin Metal ◽

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Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221109 ◽

2004 ◽

Author(s):

R. Kanamura ◽

Y. Ohoka ◽

M. Fukasawa ◽

K. Tabuchi ◽

K. Nagahata ◽

...

Keyword(s):

High Performance ◽

Hybrid Structure ◽

Dual Damascene ◽

Damascene Interconnects ◽

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A HSQ-based inorganic sacrificial via filler-assisted 90 nm-node Cu/low-k OSG dual damascene process integration

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221119 ◽

2004 ◽

Author(s):

K.-W. Lee ◽

S.G. Lee ◽

W.J. Park ◽

B.J. Oh ◽

J.H. Kim ◽

...

Keyword(s):

Process Integration ◽

Dual Damascene ◽

Damascene Process ◽

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High Performance Ultra Low-k (k=2.0/keff=2.4)/Cu Dual-Damascene Interconnect Technology with Self-Formed MnSixOy Barrier Layer for 32 nm-node

2006 International Interconnect Technology Conference ◽

10.1109/iitc.2006.1648692 ◽

2006 ◽

Author(s):

T. Usui ◽

K. Tsumura ◽

H. Nasu ◽

Y. Hayashi ◽

G. Minamihaba ◽

...

Keyword(s):

Barrier Layer ◽

High Performance ◽

Dual Damascene ◽

Interconnect Technology ◽

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High performance Al dual damascene process with elevated double stoppers

Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102) ◽

10.1109/iitc.1998.704774 ◽

2002 ◽

Author(s):

N. Nakamura ◽

M.B. Anand ◽

J. Wada ◽

Y. Oikawa ◽

T. Katata ◽

...

Keyword(s):

High Performance ◽

Dual Damascene ◽

Damascene Process

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Influence of visco-elasticity of low-k dielectrics on thermo-mechanical behavior of dual damascene process

Fifth International Conference onElectronic Packaging Technology Proceedings, 2003. ICEPT2003. ◽

10.1109/eptc.2003.1298742 ◽

2003 ◽

Author(s):

V. Gonda ◽

G.Q. Zhang ◽

J. den Toonder ◽

J. Beijer ◽

L.J. Ernst

Keyword(s):

Mechanical Behavior ◽

Dual Damascene ◽

Damascene Process ◽

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A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

2006 International Electron Devices Meeting ◽

10.1109/iedm.2006.346878 ◽

2006 ◽

Author(s):

H. Nii ◽

T. Sanuki ◽

Y. Okayama ◽

K. Ota ◽

T. Iwamoto ◽

...

Keyword(s):

High Performance ◽

Immersion Lithography ◽

Dual Damascene ◽

Platform Technology ◽

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