scholarly journals High Performance Discrete Cosine Transform Operator Using Multimedia Oriented Subword Parallelism

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Shafqat Khan ◽  
Emmanuel Casseau ◽  
Daniel Menard
Keyword(s):  
Discrete Cosine Transform ◽  
Resource Utilization ◽  
High Performance ◽  
Multimedia Applications ◽  
Utilization Rate ◽  
Two Dimensional ◽  
Cosine Transform ◽  
Subword Parallelism ◽  
Speed Up ◽  
Single Pixel

In this paper an efficient two-dimensional discrete cosine transform (DCT) operator is proposed for multimedia applications. It is based on the DCT operator proposed in Kovac and Ranganathan, 1995. Speed-up is obtained by using multimedia oriented subword parallelism (SWP). Rather than operating on a single pixel, the SWP-based DCT operator performs parallel computations on multiple pixels packed in word size input registers so that the performance of the operator is increased. Special emphasis is made to increase the coordination between pixel sizes and subword sizes to maximize resource utilization rate. Rather than using classical subword sizes (8, 16, and 32 bits), multimedia oriented subword sizes (8, 10, 12, and 16 bits) are used in the proposed DCT operator. The proposed SWP DCT operator unit can be used as a coprocessor for multimedia applications.

scholarly journals Implementation of 2D-DCT as an Efficient Accelerator for HEVC Video CODEC

2019 ◽  
Vol 9 (2) ◽  
pp. 4320-4325
Keyword(s):  
Embedded System ◽  
Discrete Cosine Transform ◽  
High Performance ◽  
Video Codec ◽  
Two Dimensional ◽  
Cosine Transform ◽  
Video Codecs ◽  
Static Power ◽  
System Requirements ◽  
Evaluation Board

Programmable architectures like GPU based embedded system for video and imaging applications are widely used due to their high performance, as they allow flexibility for running customized functions. However these architectures do not allow reconfiguration of the architecture at run time and optimization of the hardware resources. This paper explores the FPGA based architecture suitable for all video CODEC standards used in multimedia applications which is both programmable and reconfigurable. The proposed architecture demonstrates an accelerator to perform two dimensional 8*8 discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute higher order two-dimensional DCT/IDCT according to different system requirements and is implemented on Xilinx Zynq evaluation board 7vx485tffg1157-1. The architecture is found to have a high scalability in terms of power and area. The synthesis results reads, 48% improvement in both dynamic and static power consumption, with optimal hardware utilization suitable for high performance video CODECs.

A flexible high performance 2-D discrete cosine transform IC

2003 ◽  
Author(s):  
L. Matterne ◽  
D. Chong ◽  
B. McSweeney ◽  
R. Woudsma
Keyword(s):  
Discrete Cosine Transform ◽  
High Performance ◽  
Cosine Transform
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