scholarly journals Task mapping and routing optimization for hard real-time Networks-on-Chip

2019 ◽  
Vol 8 (2) ◽  
pp. 414-421 ◽  
Author(s):  
M. Norazizi Sham Mohd Sayuti ◽  
Farida Hazwani Mohd Ridzuan ◽  
Zul Hilmi Abdullah
Keyword(s):  
Real Time ◽  
Optimization Technique ◽  
Network Routing ◽  
Design Parameters ◽  
Task Mapping ◽  
Evaluation Function ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip ◽  
Hard Real Time

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.

scholarly journals Task mapping and routing optimization for hard real-time Networks-on-Chip

2019 ◽  
Vol 8 (2) ◽  
Author(s):  
M. Norazizi Sham Mohd Sayuti ◽  
Farida Hazwani Mohd Ridzuan ◽  
Zul Hilmi Abdullah
Keyword(s):  
Real Time ◽  
Task Mapping ◽  
Networks On Chip ◽  
Routing Optimization ◽  
On Chip ◽  
Hard Real Time

Evaluation of a Connectionless Technique for System-on-Chip Interconnection

2016 ◽  
Vol 25 (10) ◽  
pp. 1630005 ◽  
Author(s):  
Marcelo Daniel Berejuck ◽  
Antônio A. Fröhlich
Keyword(s):  
Real Time ◽  
High Performance ◽  
Communication Channel ◽  
Resource Reservation ◽  
Multimedia Applications ◽  
Worst Case ◽  
Average Latency ◽  
On Chip ◽  
Hard Real Time

We present the design and evaluation of a high-performance network-on-chip (NoC) focused on telecommunication and multimedia applications that tolerate latency and bandwidth variations. The design is based on a connectionless strategy in which flits from different communication flows are interleaved in the same communication channel. Each flit carries routing information that is used by routers to perform arbitration and scheduling of the corresponding output ports in order to balance channel utilization. In order to compare our approach with others, we introduce an analytic model for the worst-case latency (WCL) of our NoC and recall those of related approaches. Analytic comparisons and experimental data show that our approach keeps average WCL lower for variable-bit-rate multimedia applications than a network based on resource reservation. For these applications, the overall throughput is larger than that of networks that perform resource reservation. A case study based on the proposed NoC shows that the average latency was 28% lower than the WCL expected for the experiment. Indeed, hard real-time flows designed considering the absolute WCL of the network will always meet the requirements of the associated hard real-time tasks, so no deadline can be lost due to network contention.

Safe and efficient power management of hard real-time networks-on-chip

Integration ◽  
2019 ◽  
Vol 65 ◽  
pp. 1-17 ◽  
Author(s):  
Thawra Kadeed ◽  
Sebastian Tobuschat ◽  
Adam Kostrzewa ◽  
Rolf Ernst
Keyword(s):  
Real Time ◽  
Power Management ◽  
Networks On Chip ◽  
On Chip ◽  
Hard Real Time ◽  
Efficient Power

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

2013 ◽  
Vol 21 (10) ◽  
pp. 1823-1836 ◽  
Author(s):  
Yiyuan Xie ◽  
Mahdi Nikdast ◽  
Jiang Xu ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Networks ◽  
Case Analysis ◽  
Worst Case Analysis ◽  
Crosstalk Noise ◽  
Worst Case ◽  
Networks On Chip ◽  
On Chip

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

2014 ◽  
pp. 368-398
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Task Mapping ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
Management Measures ◽  
Mapping Process ◽  
On Chip ◽  
And Task

With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.

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