Device Model for Graphene Bilayer Field-Effect Transistor *

AbstractWe report on the extraction of carrier type, and mobility in semiconductor nanowires by adopting experimental nanowire field-effect transistor device data to a long channel MISFET device model. Numerous field-effect transistors were fabricated using n-InAs nanowires of a diameter of 50 nm as a channel. The I-V data of devices were analyzed at low to medium drain current in order to reduce the effect of extrinsic resistances. The gate capacitance is determined by an electro-static field simulation tool. The carrier mobility remains as the only parameter to fit experimental to modeled device data. The electron mobility in n-InAs nanowires is evaluated to µ = 13,000 cm2/Vs while for comparison n-ZnO nanowires exhibit a mobility of 800 cm2/Vs.

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Effect of “Mexican Hat” on Graphene Bilayer Field-Effect Transistor Characteristics

Japanese Journal of Applied Physics ◽

10.7567/jjap.50.070112 ◽

2011 ◽

Vol 50 (7R) ◽

pp. 070112 ◽

Cited By ~ 1

Author(s):

Dmitry Svintsov ◽

Vladimir Vyurkov ◽

Victor Ryzhii ◽

Taiichi Otsuji

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Graphene Bilayer ◽

Mexican Hat ◽

Effect Transistor

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Device model for poly(o-methoxyaniline) field-effect transistor

Journal of Polymer Science Part B Polymer Physics ◽

10.1002/polb.20298 ◽

2004 ◽

Vol 43 (1) ◽

pp. 74-78 ◽

Cited By ~ 19

Author(s):

R. F. Bianchi ◽

R. K. Onmori ◽

R. M. Faria

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Device Model ◽

Effect Transistor

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Silicon Carbide Junction Field Effect Transistor Compact Model for Extreme Environment Integrated Circuit Design

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2380-4491.2021.hitec.000118 ◽

2021 ◽

Vol 2021 (HiTEC) ◽

pp. 000118-000122

Author(s):

S. Perez ◽

A.M. Francis ◽

J. Holmes ◽

T. Vrotsos

Keyword(s):

Silicon Carbide ◽

Integrated Circuits ◽

Integrated Circuit ◽

Field Effect ◽

Field Effect Transistor ◽

Extreme Environment ◽

Integrated Circuit Design ◽

Device Model ◽

Effect Transistor ◽

R Process

Abstract Presented is a temperature and geometry scalable 800°C Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) compact device model designed to simulate the small signal effects of the SiC JFET-R process developed by NASA Glenn Research Center. With the JFET-R process pushing the temperature limits of integrated circuits, a high-fidelity device model capable of predicting the performance over temperature and geometry is required to realize the thermal ruggedness this process provides. A high temperature (HT) packaging system was utilized to characterize a SiC JFET device up to 800°C with a dwell time of 9 hours during a single test. Invaluable device characterization data was obtained and utilized to extend the device model presented to simulate SiC JFET performance continuously over 800°C.

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