Damages and Microstructural Variation of High-lead and Eutectic SnPb Composite Flip Chip Solder Bumps Induced by Electromigration

2005 ◽  
Vol 20 (8) ◽  
pp. 2184-2193 ◽  
Author(s):  
Yeh-Hsiu Liu ◽  
Kwang-Lung Lin
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Electron Flow ◽  
Electron Probe Microanalyzer ◽  
Current Stressing ◽  
Solder Bumps ◽  
Underbump Metallization ◽  
Current Polarity ◽  
High Lead ◽  
Eutectic Snpb

The electromigration behavior of the high-lead and eutectic SnPb composite solder bumps was investigated at 150 °C with 5 × 103 A/cm2 current stressing for up to 1711 h. The diameter of the bumps was about 125 μm. The underbump metallization (UBM) on the chip side was sputtered Al/Ni(V)/Cu thin films, and the Cu pad on the board side was plated with electroless Ni/Au. It was observed that damages occurred in the joints in a downward electron flow (from chip side to the substrate side), while those joints having the opposite current polarity showed only minor changes. In the case of downward electron flow, electromigration damages were observed in the UBM and solder bumps. The vanadium in Ni(V) layer was broken under current stressing of 1711 h while it was still intact after current stressing of 1000 h. The electron probe microanalyzer (EPMA) elemental mapping clearly shows that the Al atoms in the trace migrated through the UBM into the solder bump during current stressing. Voids were found in the solder bump near the UBM/solder interface. The Sn-rich phases of the solder bumps showed gradual streaking and reorientation upon current stressing. This resulted in the formation of uniaxial Sn-rich phases in the middle of the solder bump, while the columnar and fibrous Sn-rich phases were formed in the surrounding regions. The formation mechanism of electromigration-induced damage to the UBM structure and solder bump were discussed.

scholarly journals Relieving the current crowding effect in flip-chip solder joints during current stressing

2006 ◽  
Vol 21 (1) ◽  
pp. 137-146 ◽  
Author(s):  
S.W. Liang ◽  
T.L. Shao ◽  
Chih Chen ◽  
Everett C.C. Yeh ◽  
K.N. Tu
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Solder Joints ◽  
Three Dimensional ◽  
Current Crowding ◽  
Crowding Effect ◽  
Average Temperature ◽  
Current Stressing ◽  
Underbump Metallization ◽  
Overall Resistance

Three-dimensional simulations for relieving the current crowding effect in solder joints under current stressing were carried out using the finite element method. Three possible approaches were examined in this study, including varying the size of the passivation opening, increasing the thickness of Cu underbump metallization (UBM), and adopting or inserting a thin highly resistive UBM layer. It was found that the current crowding effect in the solder bump could be successfully relieved with the thick Cu UBM or with the highly resistive UBM. Compared to the solder joint with Al/Ni(V)/Cu UBM, for instance, the maximum current density in a solder bump decreased dramatically by a factor of fifteen, say from 1.11 × 105 A/cm2 to 7.54 × 103 A/cm2 when a 20-μm-thick Cu UBM was used. It could be lowered by a factor of seven, say to 1.55 × 104 A/cm2, when a 0.7-μm UBM of 14770 μΩ cm was adopted. It is worth noting that although a resistive UBM layer was used, the penalty on overall resistance increase was negligible because the total resistance was dominated by the Al trace instead of the solder bump. Thermal simulation showed that the average temperature increase due to Joule heating effect was only 2.8 °C when the solder joints with UBM of 14770 μΩ cm were applied by 0.2 A.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

scholarly journals Cross interactions on interfacial compound formation of solder bumps and metallization layers during reflow

2004 ◽  
Vol 19 (12) ◽  
pp. 3654-3664 ◽  
Author(s):  
T.L. Shao ◽  
T.S. Chen ◽  
Y.M. Huang ◽  
Chih Chen
Keyword(s):  
Flip Chip ◽  
Driving Forces ◽  
The Other ◽  
Compound Formation ◽  
Bump Height ◽  
Performance Requirements ◽  
Substrate Side ◽  
Solder Bumps ◽  
Snpb Solder ◽  
Eutectic Snpb

While the dimension of solder bumps keeps shrinking to meet higher performance requirements, the formation of interfacial compounds may be affected more profoundly by the other side of metallization layer due to a smaller bump height. In this study, cross interactions on the formation of intermetallic compounds (IMCs) were investigated in eutectic SnPb, SnAg3.5, SnAg3.8Cu0.7, and SnSb5 solders jointed to Cu/Cr–Cu/Ti on the chip side and Au/Ni metallization on the substrate side. It is found that the Cu atoms on the chip side diffused to the substrate side to form (Cux,Ni1−x)6Sn5 or (Niy,Cu1−y)3Sn4 for the four solders during the reflow for joining flip chip packages. For the SnPb solder, Au atoms were observed on the chip side after the reflow, yet few Ni atoms were detected on the chip side. In addition, for SnAg3.5 and SnSn5 solders, the Ni atoms on the substrate side migrated to the chip side during the reflow to change binary Cu6Sn5 into ternary (Cux,Ni1−x)6Sn5 IMCs, in which the Ni weighed approximately 21%. Furthermore, it is intriguing that no Ni atoms were detected on the chip side of the SnAg3.8Cu0.7 joint. The possible driving forces responsible for the diffusion of Au, Ni, and Cu atoms are discussed in this paper.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Direct Measurement of Hot-spot Temperature in Flip-chip Solder Joints With Cu Columns Under Current Stressing using Infrared Microscopy

2010 ◽  
Vol 1249 ◽  
Author(s):  
Chih Chen ◽  
Yu Chun Liang ◽  
D. J. Yao
Keyword(s):  
Thin Layer ◽  
Flip Chip ◽  
Solder Bump ◽  
Hot Spot ◽  
Infrared Microscopy ◽  
Column Temperature ◽  
Current Stressing ◽  
Large Current ◽  
Spot Temperature ◽  
A Current

AbstractIn this study, the temperature map distribution in the Sn3.0Ag0.5Cu solder bump with Cu column under current stressing is directly examined using infrared microscopy. It is the radiance changes between the different materials of the surface that cause the unreasonable temperature map distribution. By coating a thin layer of black optical paint which is in order to eliminate the radiance changes, we got the corrected temperature map distribution. Under a current stress of 1.15 × 104 A/cm2 at 100℃C, the hot-spot temperature is 132.2℃ which surpasses the average Cu column temperature of 129.7℃C and the average solder bump temperature of 127.4 ℃. Thermomigration in solder may still occur under a large current stressing.

A cost effective PoP structure with high I/O density

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000768-000785
Author(s):  
Hongjie Wang ◽  
Weidong Huang ◽  
Fei Geng ◽  
Yuan Lu ◽  
Bo Zhang ◽  
...  
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Solder Bump ◽  
Cost Effective ◽  
Wire Bonding ◽  
Manufacturing Cost ◽  
Good Reliability ◽  
Solder Bumps ◽  
Package Size ◽  
Interconnection Structure

Package-on-package (PoP) structure is widely used in smart phones and tablets in which memory package is directly attached to the top of the application processor. As the market demands more speed and bandwidth, memory devices need more than 1000 I/Os to support future requirements. However← since the package size also becomes smaller and smaller, finer I/O pitch is absolutely required. Although using some new technology can achieve finer I/O pitch, it increases the manufacturing cost. Using traditional mature technology can reduce manufacturing cost, but has limitation in finer I/O pitch. So, it demands a reasonable balance between design, process and cost to develop an applicable PoP structure. In this paper we proposed a novel and cost effective PoP interconnection structure and a multi-layer PoP model. The PoP interconnection was formed by the solder ball on the top package connected to the solder bumps on the bottom package. The solder bump was made of a smaller solder ball attached on a Cu stud bump on the top of bottom substrate. The Cu stud bump was made through wire bonding machines and was coined so that the small solder ball can be attached to it. Using film assist molding technology, a half of the solder ball is exposed outside of molding compound, which can be connected with the solder ball of the top package through reflow process. This PoP interconnection structure was named solder bump through molding (BTM). A three layer PoP vehicle package was designed in our experiments. The top package was a wire bonding BGA, the middle and bottom packages were both flip chip BGA with BTM interconnection structure. The package size of these three packages was 10×10mm2 and ball pitch was 0.4mm. The assembly process of top package was as normal as other wire bonding BGA. The assembly processes of middle and bottom packages were as follows: The Cu stud bumps were first bonded to the top surface of the substrate using wire bonding machines. Small solder balls were attached to the top of Cu stud bumps using stencil tool and then reflowed. After solder bumps were made, all chips were flip bonded to the substrates. Then, using film assist molding and MUF technology, the chips were encapsulated and Cu stud bumps were half exposed. After all the packages were ready, the package stacking and reflow was performed one by one from top to the bottom and the overall three layer PoP was formed. C-scan test and cross section analysis showed that the encapsulation had no voids in most samples. Electrical test results showed the interconnection was good. Reliability study will be also discussed in this paper, which is still in research now. In BTM structure, both Cu stud and solder ball attach can be easily realized. The ball pitch can be 0.4mm or smaller and the process is also applicable for more layer PoP. Thus, BTM PoP structure provides a good solution considering the balance among cost, performance and manufacturing for 3D package. Acknowledgments The authors acknowledge the support of National Science and Technology Major Project (Project number：2013ZX02501003).

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