Chip-to-Module Interconnections Using “Sea of Leads” Technology

MRS Bulletin ◽  
2003 ◽  
Vol 28 (1) ◽  
pp. 61-67 ◽  
Author(s):  
Muhannad S. Bakir ◽  
Hollie A. Reed ◽  
Anthony V. Mulé ◽  
Joseph Paul Jayachandran ◽  
Paul A. Kohl ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Optical Interconnects ◽  
High Performance ◽  
Index Of Refraction ◽  
Wafer Level ◽  
Enabling Technology ◽  
Air Gaps ◽  
The Core ◽  
Mechanical Compliance ◽  
Ultrahigh Density

AbstractThe drive toward higher density and higher performance in integrated circuits creates a need to keep interconnects short and eliminate layers of packaging. In this article, we propose a novel, ultrahigh-density (exceeding 104 leads per cm2), compliant, wafer-level, input/output interconnection technology called “sea of leads” as a key enabling technology for future high-performance microsystems. The mechanical compliance is addressed through slippery leads (leads released from the surface) and embedded air gaps. The ability to fabricate embedded air gaps has enabled the integration of optical interconnects with high index-of-refraction mismatches between the core and cladding.

A Lithography-Based Compliant Chip-to-Substrate Wafer-Level Interconnect

2002 ◽  
Author(s):  
Qi Zhu ◽  
Lunyu Ma ◽  
Suresh K. Sitaraman
Keyword(s):  
High Performance ◽  
Coefficient Of Thermal Expansion ◽  
Low Cost ◽  
Optimization Technique ◽  
Cost Effective ◽  
Organic Substrate ◽  
Electrical Performance ◽  
Wafer Level ◽  
Good Reliability ◽  
Mechanical Compliance

As the rapid advances in IC design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great advantages for next-generation packaging. β-fly is designed as a compliant chip-to-substrate interconnect for performing wafer-level probing and for packaging without underfill. β-fly has good compliance in all directions to compensate the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of β-fly is similar to standard IC fabrication, and wafer-level packaging makes it cost effective. In this work, self-weight effect and stress distribution under planar displacement loading of β-fly is studied. The effect of geometry parameters on mechanical and electrical performance of β-fly is also studied. β-fly with thinner and narrower arcuate beams with larger radius and taller post is found to have better mechanical compliance. In addition to mechanical compliance, electrical characteristics of β-fly have also been studied in this work. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of β-fly. Response surface methodology and an optimization technique have been used to select the optimal β-fly structure parameters.

50 GHz S-shaped rat-race balun with 1.4 dB insertion loss in a wafer-level chip-size package process

2009 ◽  
Vol 1 (4) ◽  
pp. 347-352
Author(s):  
Ahmet Oncu ◽  
Chiaki Inui ◽  
Yasuo Manzawa ◽  
Minoru Fujishima
Keyword(s):  
Integrated Circuits ◽  
Insertion Loss ◽  
Silicon On Insulator ◽  
Cmos Circuits ◽  
Wafer Level ◽  
Chip Area ◽  
The Core ◽  
Chip Size ◽  
Differential Circuits ◽  
On Chip

In millimeter-wave CMOS circuits, a balun is useful for connecting off-chip single-end devices and on-chip differential circuits to improve noise immunity. However, an on-chip balun occupies a large chip area. To reduce the chip area required for the on-chip balun, a new rat-race balun using a rewiring technology with a wafer-level chip-size package (W-CSP) is proposed. The W-CSP balun occupies no area in a die because it is placed over integrated circuits. In the proposed balun, an S-shaped structure is adopted in order to directly connect the balun to differential GSGSG pads on a chip with a small area. The S-shaped W-CSP balun was fabricated on a silicon-on-insulator (SOI) substrate. The core area of the S-shaped rat-race balun is 480×735 µm, which is 22.4% that of a square rat-race balun. As a result of measurement, we found that the minimum insertion loss is 1.4 dB and the operating frequency ranges from 40 to 61 GHz.

Compliant Wafer Level Package

2001 ◽  
Author(s):  
Chirag Patel ◽  
Kevin P. Martin ◽  
James D. Meindl
Keyword(s):  
Performance Analysis ◽  
Integrated Circuits ◽  
High Performance ◽  
Wafer Level ◽  
Electronic Products ◽  
Packaging Technology ◽  
Technology Roadmap ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Wafer Level Package

Abstract A high I/O density and high performance wafer level packaging technology called the Compliant Wafer Level Package (CWLP) is reported. The necessity for compliant interconnects in upcoming generations of electronic products is discussed by analyzing the technology requirements projected by the International Technology Roadmap for Semiconductors (ITRS). To be a true wafer level package, the technology should have following three characteristics11: I) package all Integrated Circuits (ICs) intact on wafer at once, II) perform wafer level test and burn-in, and III) assemble the WLP on the system board without using an underfill. Compliant interconnects are essential to accomplishing wafer level test and assembly without underfill. These topics are discussed in the paper followed by fabrication and performance analysis of the CWLP technology.

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

Fluorocarbon Precursor for High Aspect Ratio via Milling in Focused Ion Beam Modification of Integrated Circuits

2004 ◽  
Author(s):  
Valery Ray
Keyword(s):  
Side Effects ◽  
Aspect Ratio ◽  
Integrated Circuits ◽  
High Aspect Ratio ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Enabling Technology ◽  
Si Substrate ◽  
Ion Beam Modification ◽  
The Past

Abstract Gas Assisted Etching (GAE) is the enabling technology for High Aspect Ratio (HAR) circuit access via milling in Focused Ion Beam (FIB) circuit modification. Metal interconnect layers of microelectronic Integrated Circuits (ICs) are separated by Inter-Layer Dielectric (ILD) materials, therefore HAR vias are typically milled in dielectrics. Most of the etching precursor gases presently available for GAE of dielectrics on commercial FIB systems, such as XeF2, Cl2, etc., are also effective etch enhancers for either Si, or/and some of the metals used in ICs. Therefore use of these precursors for via milling in dielectrics may lead to unwanted side effects, especially in a backside circuit edit approach. Making contacts to the polysilicon lines with traditional GAE precursors could also be difficult, if not impossible. Some of these precursors have a tendency to produce isotropic vias, especially in Si. It has been proposed in the past to use fluorocarbon gases as precursors for the FIB milling of dielectrics. Preliminary experimental evaluation of Trifluoroacetic (Perfluoroacetic) Acid (TFA, CF3COOH) as a possible etching precursor for the HAR via milling in the application to FIB modification of ICs demonstrated that highly enhanced anisotropic milling of SiO2 in HAR vias is possible. A via with 9:1 aspect ratio was milled with accurate endpoint on Si and without apparent damage to the underlying Si substrate.

scholarly journals Acoustic Panels Made of Paper Sludge and Clay Composites

2021 ◽  
Vol 13 (2) ◽  
pp. 637
Author(s):  
Tomas Astrauskas ◽  
Tomas Januševičius ◽  
Raimondas Grubliauskas
Keyword(s):  
Absorption Coefficient ◽  
Sound Absorption ◽  
Composite Panel ◽  
Sound Absorption Coefficient ◽  
Core Material ◽  
Paper Sludge ◽  
Frequency Range ◽  
Absorption Properties ◽  
Air Gaps ◽  
The Core

Studies on recycled materials emerged during recent years. This paper investigates samples’ sound absorption properties for panels fabricated of a mixture of paper sludge (PS) and clay mixture. PS was the core material. The sound absorption was measured. We also consider the influence of an air gap between panels and rigid backing. Different air gaps (50, 100, 150, 200 mm) simulate existing acoustic panel systems. Finally, the PS and clay composite panel sound absorption coefficients are compared to those for a typical commercial absorptive ceiling panel. The average sound absorption coefficient of PS-clay composite panels (αavg. in the frequency range from 250 to 1600 Hz) was up to 0.55. The resulting average sound absorption coefficient of panels made of recycled (but unfinished) materials is even somewhat higher than for the finished commercial (finished) acoustic panel (αavg. = 0.51).

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