Properties of Graphite Interconnect Circuit Boards with Anisotropic Thermal Expansion

1990 ◽  
Vol 216 ◽  
Author(s):  
J. Malamas ◽  
R.P. Bambha ◽  
J.B. Ramsey ◽  
W.C. Garrett ◽  
E.G. Kelso ◽  
...  
Keyword(s):  
Thin Films ◽  
Electrical Conductivity ◽  
Thermal Expansion ◽  
Focal Plane ◽  
Thermal Stresses ◽  
Focal Plane Arrays ◽  
Circuit Board ◽  
Circuit Boards ◽  
Anisotropic Thermal Expansion ◽  
Indium Bump

ABSTRACTWe report the investigation of an interconnect circuit board (ICB) with anisotropic thermal expansion for use with bump bonded, indirect hybrid, scanning focal plane arrays. This ICB is designed to reduce significantly the thermal stresses on the indium bump bonds during thermal cycling. Highly oriented pyrolitic graphite (HOPG) was chosen because its anisotropic thermal expansion meets the criteria for forming an indirect hybrid ICB using silicon processor circuits and mecury cadmium telluride detectors. Properties of HOPG influencing its performance as an ICB have been investigated including thermal expansion, electrical conductivity, durability, and adherence of electrically insulating thin films.

Preparation of (Ba0.67Sr0.33)TiO3 Thin Films for the Dielectric Bolometer Mode of Uncooled Infrared Focal Plane Arrays

2002 ◽  
Vol 194 (1) ◽  
pp. 64-70 ◽  
Author(s):  
Shi-jian Liu ◽  
Chong-yang Xu ◽  
Xiang-bin Zeng ◽  
Ji-qun Shi ◽  
Bo-fang Zhao
Keyword(s):  
Thin Films ◽  
Focal Plane ◽  
Focal Plane Arrays ◽  
Infrared Focal Plane Arrays

Fatigue Analysis of a Ceramic Pin Grid Array Soldered to an Orthotropic Epoxy Substrate

1991 ◽  
Vol 113 (2) ◽  
pp. 138-148 ◽  
Author(s):  
J. Lau ◽  
R. Subrahmanyan ◽  
D. Rice ◽  
S. Erasmus ◽  
C. Li
Keyword(s):  
Thermal Expansion ◽  
Solder Joint ◽  
Normal Stress ◽  
Printed Circuit Board ◽  
Thermal Stresses ◽  
Circuit Board ◽  
Thermal Expansion Mismatch ◽  
Stress Strain ◽  
Plated Through Hole ◽  
Through Hole

Thermal stresses and strains in the solder joints and plated-through-hole (PTH) copper pads/barrels of a pin-grid array (PGA) assembly under thermal cycling conditions have been determined in the present study. There are two major systems of thermal stresses/strains acting at the solder joint and copper. One is the transverse shear and vertical normal stress/strain due to the local thermal expansion mismatch between the pin, solder, copper, and FR-4. The other is the horizontal normal stress/strain due to the global thermal expansion mismatch between the ceramic PGA and the FR-4 printed circuit board (PCB). The effects of the local thermal expansion mismatch on the reliability of solder joint and PTH copper have been determined using a 3-D orthotropic-elastoplastic finite element method. The effects of the global thermal expansion mismatch on the reliability of solder joint and PTH copper have been determined by fatigue experiments. Fatigue life of the solder joint and PTH copper was then estimated based on the calculated strains and the fatigue data on solders and coppers.

Recent advances in heteroepitaxial Ge/Si(100) and Ge/Si(l 11)

1994 ◽  
Vol 52 ◽  
pp. 838-839
Author(s):  
J. B. Posthill ◽  
D. P. Malta ◽  
R. Pickett ◽  
M. L. Timmons ◽  
T. P. Humphreys ◽  
...  
Keyword(s):  
Focal Plane ◽  
High Mobility ◽  
Epitaxial Films ◽  
Focal Plane Arrays ◽  
Si Substrate ◽  
Large Area ◽  
Lattice Match ◽  
Temperature Growth ◽  
X Ray ◽  
Indium Bump

Heteroepitaxial Ge-on-Si could have many applications which include: high mobility p-channel fieldeffect transistors (FETs), large area Ge-based IR or X-ray detectors, or as a substrate for the growth of other epitaxial semiconductors. In particular, the close lattice match between Ge and GaAs and Ge and ZnSe offers a potential for Ge to be used as an interlayer for a GaAs/Si or ZnSe/Si technology.Additionally, with the Si substrate as the "foundation" for further epitaxial semiconductors, thereisa built-in thermal match for any device that must be intimately bonded to Si-based circuitry. Thisis particularly critical in the case of HgCdTe IR focal plane arrays that are indium bump-bonded to aSi multiplexer which will experience thermal cycling in use. This contribution briefly reviews some ofour recent results in the high temperature growth of Ge epitaxial films on Si(100) and Si(l 11) substrates which are being developed for use as a template for HgCdTe/CdZnTe growth.

Negative, anisotropic thermal expansion in monolithic thin films of crystalline metal-organic frameworks

2016 ◽  
Vol 222 ◽  
pp. 241-246 ◽  
Author(s):  
Zhengbang Wang ◽  
Peter G. Weidler ◽  
Carlos Azucena ◽  
Lars Heinke ◽  
Christof Wöll
Keyword(s):  
Thin Films ◽  
Thermal Expansion ◽  
Metal Organic Frameworks ◽  
Anisotropic Thermal Expansion ◽  
Metal Organic ◽  
Crystalline Metal

Mounting Leadless Chip Carriers onto Printed Circuit Boards

1982 ◽  
Vol 1 (1) ◽  
pp. 38-43 ◽  
Author(s):  
D. Fishman ◽  
N. Cooper
Keyword(s):  
Thermal Expansion ◽  
Thermal Cycling ◽  
Printed Circuit Boards ◽  
Coefficient Of Thermal Expansion ◽  
Cycling Performance ◽  
Circuit Board ◽  
Circuit Boards ◽  
Acceptable Solution ◽  
Printed Circuit ◽  
Chip Carrier

It is reasoned that wide penetration of chip carriers into equipment for professional and commercial applications depends on developing methods for mounting the leadless types directly on to conventional polymer type printed circuit boards. The main problem to be overcome is fatigue failure of the solder joints due to the mismatch in thermal expansion, evidenced by poor thermal cycling performance. In this paper the thermal cycling performance is compared when four sizes of ceramic leadless chip carrier are mounted on a selection of printed circuit board materials ranging from the conventional to those specially formulated, either on the basis of matching the coefficient of thermal expansion of the chip carrier material, or to provide a layer of compliant elastomer material underneath the layer bearing the copper contact layer, so that strain due to thermal expansion mismatch is not transmitted to the solder layer. Over 400 thermal cycles (−55 to + 125°C) were recorded using proprietary versions of elastomer coated substrates. For appropriate applications the basis is thus laid for an economic and technically acceptable solution. The practical implications of two methods of soldering—wave (jet) and vapour phase—are also discussed.

scholarly journals Modeling of the ecological separation process of printed circuit boards

2018 ◽  
Vol 210 ◽  
pp. 01004 ◽  
Author(s):  
Dagmar Janačová ◽  
Vladimír Vašek ◽  
Ján Pitel’ ◽  
Miluše Vítečková ◽  
Rudolf Drga ◽  
...  
Keyword(s):  
Printed Circuit Boards ◽  
Printed Circuit Board ◽  
Thermal Stresses ◽  
Circuit Board ◽  
Temperature Fields ◽  
Circuit Boards ◽  
Simulation Experiments ◽  
Modeling Tools ◽  
Printed Circuit ◽  
Temperature Separation

The content of this paper is the modeling of the stress in the printed circuit board due to the cyclic thermal stress for its ecological recycling. Cyclic thermal stresses result in separation of copper conduction paths and plastic plates due to different longitudinal expansion. For separation, it was important to determine the minimum temperature of the cyclical changes to separate the conductive copper paths and the plastic. We use mathematical modeling tools to describe the course of temperature fields in the PCB during heating and reheating. We conducted some simulation experiments in the Pro/ENGINEER programming environment to know the waveforms and stresses of the PCBs during the cyclic loading cycle. From experiments conducted in the laboratory, we have verified that the process of temperature separation is feasible for designing an eco-friendly way of recycling PCBs.

Advanced Methodologies for Developing Improved Potted Smart Munitions for High-G Applications

2013 ◽  
Vol 135 (3) ◽  
Author(s):  
Nien-Hua Chao ◽  
John A. Dispenza ◽  
Mario DeAngelis
Keyword(s):  
Thermal Expansion ◽  
Thermal Management ◽  
Thermal Stresses ◽  
Coefficient Of Thermal Expansion ◽  
Barrier Properties ◽  
Temperature Cycling ◽  
Circuit Board ◽  
Polymer Layer ◽  
Interference Control ◽  
Protective Polymer

Potted electronics are becoming more common in precision-guided smart munitions designs due to the requirements for miniaturization and structural-robustness. In most of these applications, the potted electronics are inactive for most of their lifetime and may be stored without environmental (temperature and humidity) controls for up to 20 yr. The uncontrolled environment for smart munitions however makes the thermal management task especially difficult due to the coefficient of thermal expansion (CTE) mismatch that can exist between the potting material and the electronic components. In this paper, we will do the following: (1) present a methodology being developed for reducing the thermal stresses to the potted electronics used in uncontrolled environments by encapsulating the circuit board assembly (CBA) with a thin polymer layer which has been precisely formed to conform to the imprecisely shaped, as-populated, CBA. The protective polymer layer will be both flexible and soft enough to protect the CBA components from damage caused by thermal expansion mismatches, but not degrade the structural support that the potting provides during high-g force projectile launches, (2) discuss how the protective polymer layer methodology can also be used to lessen in-circuit board crosstalk, improve shielding from external RF interference, control tin-whisker growth, and enhance moisture barrier properties and thermal management for CBAs, and (3) demonstrate how to improve the smart munitions survivability under extreme high-g applications through the use of syntactic foams and material characterization before and after accelerated temperature-cycling and thermal-aging tests.

scholarly journals Effect of Thermal Stresses Formed during Air Annealing of Amorphous Lanthanum Cuprate Thin Films Deposited on Silicon Substrate

Coatings ◽  
2020 ◽  
Vol 10 (7) ◽  
pp. 613 ◽  
Author(s):  
Nolwenn Tranvouez ◽  
Philippe Steyer ◽  
Annie Malchère ◽  
Pascal Boulet ◽  
Fabien Capon ◽  
...  
Keyword(s):  
Thin Films ◽  
Thermal Expansion ◽  
Thermal Expansion Coefficient ◽  
Expansion Coefficient ◽  
Thermal Stresses ◽  
Environmental Scanning Electron Microscopy ◽  
X Ray Diffraction ◽  
X Ray ◽  
Lift Off

Amorphous thin films of La–Cu–O deposited by magnetron sputtering have been annealed at different temperatures and in situ analyzed by X-ray diffraction. These experiments were useful to determine the crystallization temperature and to follow the crystallization process of the film. The in situ annealing X-ray diffraction analyses have been also used to determine the thermal expansion coefficient of La2CuO4 thin film. The estimated value is close to that obtained for a commercial powder. The thermal expansion coefficient value with additional environmental scanning electron microscopy observations explains the delamination origin that occurs during the annealing before the crystallization step. The buckling and delamination of the film observed is caused by the thermal expansion coefficient mismatch of the film and the substrate. During the heating step, the mismatch generates compressive stress at the film/substrate interface, causing the film to lift off and crack in the typical way.

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