A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping

2019 ◽  
Author(s):  
Chen-Kai Hsu ◽  
Nan Sun
Keyword(s):  
Sar Adc ◽  
Gain Error

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping

2020 ◽  
pp. 1-1
Author(s):  
Chen-Kai Hsu ◽  
Xiyuan Tang ◽  
Jiaxin Liu ◽  
Rui Xu ◽  
Wenda Zhao ◽  
...  
Keyword(s):  
Sar Adc ◽  
Quantization Noise ◽  
Noise Shaping ◽  
Gain Error

A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping

2020 ◽  
Vol 55 (4) ◽  
pp. 1032-1042
Author(s):  
Chen-Kai Hsu ◽  
Timothy R. Andeen ◽  
Nan Sun
Keyword(s):  
Second Order ◽  
Sar Adc ◽  
Gain Error

Inter-Stage Gain Error self-calibration of a 31.5fJ 10b 470MS/S Pipelined-SAR ADC

2012 ◽  
Author(s):  
Jianyu Zhong ◽  
Yan Zhu ◽  
Sai-Weng Sin ◽  
U Seng-Pan ◽  
Rui Paulo Martins
Keyword(s):  
Sar Adc ◽  
Self Calibration ◽  
Gain Error

SAR ADC Algorithm With Redundancy Using Pseudo-Silver-Ratio

2017 ◽  
Vol 137 (2) ◽  
pp. 222-228
Author(s):  
Yutaro Kobayashi ◽  
Takuya Arafune ◽  
Shohei Shibuya ◽  
Haruo Kobayashi
Keyword(s):  
Sar Adc

13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS

2021 ◽  
Author(s):  
Gerd Kiene ◽  
Alessandro Catania ◽  
Ramon Overwater ◽  
Paolo Bruschi ◽  
Edoardo Charbon ◽  
...  
Keyword(s):  
Quantum Computing ◽  
Sar Adc
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