scholarly journals Design and Implementation of a System-on-Chip for Self-Calibration of an Angular Position Sensor

2019 ◽  
Vol 9 (22) ◽  
pp. 4772 ◽  
Author(s):  
Zhenyi Gao ◽  
Bin Zhou ◽  
Chao Li ◽  
Bo Hou ◽  
Haobo Sun ◽  
...  

In this study, a novel signal processing algorithm and hardware processing circuit for the self-calibration of angular position sensors is proposed. To calibrate error components commonly found in angular position sensors, a parameter identification algorithm based on the least mean square error demodulation is developed. A processor to run programs and a coprocessor based on the above algorithm are used and designed to form a System-on-Chip, which can calibrate signals as well as implement parameter configuration and control algorithm applications. In order to verify the theoretical validity of the design, analysis and simulation verification of the scheme are carried out, and the maximum absolute error value in the algorithm simulation is reduced to 0.003 %. The circuit’s Register-Transfer Level simulation shows that the maximum absolute value of the angular error is reduced to 0.03%. Simulation results verify the calibration performance with and without quantization and rounding error, respectively. The entire system is prototyped on a Field Programmable Gate Array and tested on a Capacitive Angular Position Sensor. The proposed scheme can reduce the absolute value of angular error to 4.36%, compared to 7.68% from the experimental results of a different calibration scheme.

Sensors ◽  
2019 ◽  
Vol 19 (12) ◽  
pp. 2760 ◽  
Author(s):  
Gao ◽  
Zhou ◽  
Hou ◽  
Li ◽  
Wei ◽  
...  

This study proposes a novel model-based automatic search algorithm to realize the self-calibration of nonlinear signal model for angular position sensors. In some high-precision angular position sensors, nonlinearity of the signal model is the main source of errors and cannot be handled effectively. By constructing a signal flow network framework and by embedding a modeling search network, the parameters of the nonlinear signal model can be searched, and the calibration signal can be obtained. The convergence of the network search process was analyzed. The relationship between the optimization threshold and the convergence accuracy was also studied in simulations. Compared with the maximum angular error reduction to 47.42% after the calibration with simplified model that ignores signal nonlinearities, the proposed scheme was able to reduce this error to 0.0025% in simulations. By implementing the technique in a capacitive angular position sensor, the experimental results showed that the maximum angular error was reduced to 1.63% compared to a reduction of 86.02% achieved with the simplified model calibration. The effects of the search network order and layer number on the calibration accuracy were also analyzed, and the optimal parameters under experimental conditions were obtained. Correspondingly, the proposed scheme is able to handle calibration of nonlinear signal model and further improve sensor accuracy.


2019 ◽  
Vol 19 (14) ◽  
pp. 5446-5453 ◽  
Author(s):  
Pinggui Luo ◽  
Qifu Tang ◽  
Huan Jing ◽  
Xihou Chen

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 431
Author(s):  
Zhenyi Gao ◽  
Bin Zhou ◽  
Xiang Li ◽  
Lei Yang ◽  
Qi Wei ◽  
...  

Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.


Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors


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