A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

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A continuous-time cascaded delta-sigma modulator with PMW-based automatic RC time constant tuning and correlated double sampling

Microelectronics Journal ◽

10.1016/j.mejo.2013.03.001 ◽

2013 ◽

Vol 44 (5) ◽

pp. 431-441 ◽

Cited By ~ 2

Author(s):

Bing Li ◽

Kong-Pang Pun

Keyword(s):

Time Constant ◽

Continuous Time ◽

Double Sampling ◽

Delta Sigma Modulator ◽

Correlated Double Sampling ◽

Delta Sigma ◽

Rc Time Constant

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The Delta-Sigma Modulator of Fractional-N Frequency Synthesizer for Wireless Sensors Network Applications

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.609-610.1014 ◽

2014 ◽

Vol 609-610 ◽

pp. 1014-1019 ◽

Cited By ~ 1

Author(s):

Zhi Qiang Gao ◽

Jin Bao Lan ◽

Xiao Wei Liu ◽

Liang Yin

Keyword(s):

Frequency Synthesizer ◽

Linear Feedback ◽

Cmos Process ◽

Noise Shaping ◽

Network Applications ◽

Delta Sigma Modulator ◽

Multi Stage ◽

Delta Sigma ◽

Third Stage ◽

Feedback Shift Register

This paper presents a design of fractional-N frequency synthesizer with low dithering, which is fabricated in a 130nm CMOS process. A 3rd-order delta-sigma modulator is based on digital multi-stage noise shaping (MASH) structure with its second and third stage dithered by 7-bit linear feedback shift register (LFSR) was designed for the frequency synthesizer, and a long word is used for the first modulator in the MASH structure. The simulation result of the whole frequency synthesizer shows that it can output two-way I/Q signal between 2.28GHz and 2.53GHz, and its spurs are lower than-75dBc.

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Delta-Sigma Modulator with Relaxed Feedback Timing for High Speed Applications

Electronics ◽

10.3390/electronics8101138 ◽

2019 ◽

Vol 8 (10) ◽

pp. 1138

Author(s):

Youngho Jung ◽

Jooyoung Jeon

Keyword(s):

Power Dissipation ◽

High Speed ◽

Cmos Process ◽

Dynamic Element Matching ◽

Analog To Digital ◽

Feedback Timing ◽

Delta Sigma Modulator ◽

Delta Sigma ◽

Circuit Technique ◽

Signal Band

In this paper, a ΔΣ analog-to-digital converter (ADC) was designed and measured for broadband and high-resolution applications by applying the simple circuit technique to alleviate the feedback timing of input feed-forward architecture. With the proposed technique, a low-speed comparator and dynamic element matching (DEM) logic can be applied even for high-speed implementation, which helps to decrease power dissipation. Two prototypes using slightly different input branch topologies were fabricated with a 0.18 um 2-poly and 4-metal CMOS process, and measured to demonstrate the effectiveness of the proposed circuit technique. The sampling capacitor and feedback DAC capacitors were separated in prototype A, while they were shared in prototype B. The prototypes achieved 81.2 dB and 72.4 dB of SNDR in a 2.1 MHz signal band, respectively.

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