scholarly journals Cavity-BOX SOI: Advanced Silicon Substrate with Pre-Patterned BOX for Monolithic MEMS Fabrication

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 414
Author(s):  
Marta Maria Kluba ◽  
Jian Li ◽  
Katja Parkkinen ◽  
Marcus Louwerse ◽  
Jaap Snijder ◽  
...  

Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

2010 ◽  
Vol 7 ◽  
pp. 98-108
Author(s):  
Yu.A. Gafarova

To solve problems with complex geometry it is considered the possibility of application of irregular mesh and the use of various numerical methods using them. Discrete analogues of the Beltrami-Mitchell equations are obtained by the control volume method using the rectangular grid and the finite element method of control volume using the Delaunay triangulation. The efficiency of using the Delaunay triangulation, Voronoi diagrams and the finite element method of control volume in a test case is demonstrated.


Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 382
Author(s):  
Chao Xiang ◽  
Yulan Lu ◽  
Chao Cheng ◽  
Junbo Wang ◽  
Deyong Chen ◽  
...  

This paper presents a resonant pressure microsensor with a wide range of pressure measurements. The developed microsensor is mainly composed of a silicon-on-insulator (SOI) wafer to form pressure-sensing elements, and a silicon-on-glass (SOG) cap to form vacuum encapsulation. To realize a wide range of pressure measurements, silicon islands were deployed on the device layer of the SOI wafer to enhance equivalent stiffness and structural stability of the pressure-sensitive diaphragm. Moreover, a cylindrical vacuum cavity was deployed on the SOG cap with the purpose to decrease the stresses generated during the silicon-to-glass contact during pressure measurements. The fabrication processes mainly contained photolithography, deep reactive ion etching (DRIE), chemical mechanical planarization (CMP) and anodic bonding. According to the characterization experiments, the quality factors of the resonators were higher than 15,000 with pressure sensitivities of 0.51 Hz/kPa (resonator I), −1.75 Hz/kPa (resonator II) and temperature coefficients of frequency of 1.92 Hz/°C (resonator I), 1.98 Hz/°C (resonator II). Following temperature compensation, the fitting error of the microsensor was within the range of 0.006% FS and the measurement accuracy was as high as 0.017% FS in the pressure range of 200 ~ 7000 kPa and the temperature range of −40 °C to 80 °C.


2021 ◽  
Vol 255 ◽  
pp. 01003
Author(s):  
Kevan K. MacKayt ◽  
Winnie N. Ye

A novel broadband multimode waveguide bend is proposed that supports the propagation of multiple TE modes on a silicon-on-insulator platform. The gradient curvature bend utilizes trapezoidal subwavelength grating (SWG) segments, connected by adiabatically tapered radial strips to achieve efficient mode (de)multiplexing. The inclusion of the radial strips offers an extra degree of design freedom, allowing the realization of a multimode bend with only one single full etch step. The access waveguide has a width of 2.075 μm with an effective radius of 10 μm. Propagation loss for all modes remains below 2.96 dB, and intermodal crosstalk has a maximum of -19 dB across a broad bandwidth of 100 nm, centred at 1550 nm. This work presents an excellent design choice for broadband mode-division multiplexing operations.


2021 ◽  
Author(s):  
Clement Cointe ◽  
Adrian Laborde ◽  
Lionel G Nowak ◽  
David Bourrier ◽  
Christian Bergaud ◽  
...  

Flexible deep brain probes have been the focus of many research works and aims at achieving better compliance with the surrounding brain tissue while maintaining minimal rejection. Strategies have been explored to find the best way to implant a flexible probe in the brain, while maintaining its flexibility once positioned in the cortex. Here, we present a novel and versatile scalable batch fabrication approach to deliver ultra-thin and flexible penetrating neural probe consisting of a silk-parylene bilayer. The biodegradable silk layer provides a temporary and programmable stiffener to ensure ease of insertion of the ultrathin parylene-based flexible devices. The innovative and yet robust batch fabrication technology allows complete design freedom of the neural probe in terms of materials, size, shape and thickness. These results provide a novel technological solution for implanting ultra-flexible and ultrathin devices, which possesses great potential for brain research.


2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001851-001892
Author(s):  
Thibault Buisson

MEMS are found in many applications, ranging from large volume consumer applications such as mobile phones to specific high end devices for defense or space. MEMS market will continue to see steady, sustainable double digit growth for the next six years, with 20% compound average annual growth in units and 13% growth in revenues, to become a $21 billion market by 2017. Automotive applications represent today around 20% of the MEMS market in revenue and are expected to see a 5.4 % growth in the next five years, which means that the penetration of MEMS devices in this market will remain limited. Today, MEMS family in cars is mainly represented by pressure sensors for Tire Pressure Monitoring and Manifold Air Pressure sensing, and accelerometers in ABS and stabilization systems. These applications are reaching maturity, which mean that their growth gets directly related to the car sales. To find new growth opportunities, system integrators have been trying to develop new MEMS based systems to enhance safety, comfort and reduce pollution and energy consumption. The presentation will show emerging applications and the challenges they face from a technical and a market point of view. Diverse electronic packages operate under exceptionally harsh environments, which require extended lifetimes, presenting a significant challenge for the microelectronics community. Operating temperatures above 200 °C together with high pressures, vibrations and potentially corrosive environments implies that some technical issues regarding the development of electronic systems that will operate at such high temperature remain. Technology based on sintering has been recently emerging for power modules, capable of withstanding up to 300 °C. Sintered Ag is one potential candidate for die attachment for extreme environments. The application of sintered Ag has proven already to significantly increase the lifetime of interconnects when compared to solder joints. Both characterization of the failure mechanisms as well as prediction of product life in such environments is critical to the long term reliability of these devices. The present work aims to develop an understanding of how and why attach materials for Si dies degrade/fail under harsh environments by investigating sintered Ag material. New failure mechanisms will become dominant in the sintered Ag technology. Modeling helps understanding how a particular system behaves if conditions are altered. Thus, a 2D axis symmetric die attach model, commonly used to represent microelectronic package assemblies, was generated using Ansys Workbench. The FE-model provided a good understanding of the effect of single parameter variation of different leadframe materials (K64, K14, and FeNi42), chip height, sintered Ag and metallization thicknesses. The FE-model provided a rapid assessment of delamination, cracking and other defects and their location within the package. The effect of the sintered Ag thickness on the plastic strain was only slight. Furthermore, on the chip side, the local thermal mismatch between the Si die and the sintered Ag was the most important loading factor. Also, thicker chips generated higher stresses. Further analysis of simulation and experiment of sintered Ag interconnects will give more insight on dominating failure mechanisms, and help reduce failure risks.


2006 ◽  
Vol 326-328 ◽  
pp. 529-532
Author(s):  
Sung Hoon Choa ◽  
Moon Chul Lee ◽  
Yong Chul Cho

In MEMS, packaging induced stress or stress induced structure deformation becomes increasing concerns since it directly affects the performance of the device. The conventional MEMS SOI (silicon-on-insulator) gyroscope, packaged using the anodic bonding at the wafer level and EMC (epoxy molding compound) molding, has a deformation of MEMS structure caused by thermal expansion mismatch. Therefore we propose a packaged SiOG (Silicon On Glass) process technology and more robust spring design.


Author(s):  
Harita Machiraju ◽  
Bill Infantolino ◽  
Bahgat Sammakia ◽  
Michael Deeds

A MEMS based device consisting of microactuators was modeled using finite element analysis. The temperature profile of the complete package was obtained and compared to experimental measurements. Good agreement was found between the modeling and measurements. Parametric studies of potential design parameters of the chip package to decrease the power requirements to the actuators have been studied. Increasing the gap between the handle layer and the device layer of the SOI (silicon on insulator) chip from 2 to 3 microns resulted in a reduction of 10% (0.2 Watts) per beam of the actuator. A glass top chip proved to be better at reducing the power requirements for the actuators when compared to a silicon top chip. Modeling shows that relief cuts in the substrate had a larger effect on the power reduction compared to those on the top chip since the heat conduction path to the substrate is a lower resistance path. The power reduction was as high as 50% (1.1 Watts) per beam of the actuator, when the relief cut in the substrate was 50 microns.


1996 ◽  
Vol 446 ◽  
Author(s):  
G. G. Li ◽  
A. R. Forouhi ◽  
I. Bloomer ◽  
A. Auberton-Herve ◽  
A. Wittkower

AbstractA new technique, referred to as the “n&k Method”, is used to characterize the thin films comprising Silicon-on-Insulator (SOI). With the “n&k Method”, a non-destructive robust measurement of the thickness of both the crystalline silicon top-layer and the buried oxide under-layer, the spectra of refractive index (n), and extinction coefficient (k), and the smoothness of the interfaces is established. The “n&k Method” determines these quantities simultaneously and without multiple solutions for thickness. The non-destructive measurement of interface roughness between the buried oxide under-layer and the silicon substrate is associated with the presence of silicon islands. The native oxide that forms on SOI is also detected and measured. No initial user's input for thickness and optical constants are required in order to obtain these results. The spectra of optical constants are measured accurately and reliably.


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