scholarly journals Low Power Oriented Full Search Block Based Motion Estimation (LP-FSBME) Architecture Using Power Efficient Adder Compressor For H.265 Coding Techniques.

2019 ◽  
Vol 9 (1S) ◽  
pp. 67-71
Keyword(s):  
Motion Estimation ◽  
Low Power ◽  
Video Coding ◽  
High Efficiency ◽  
Video Quality ◽  
Motion Vector ◽  
Absolute Difference ◽  
Power Efficient ◽  
Block Based ◽  
Full Search

H.265 coding is known as HIGH efficiency video coding (HEVC). This is most successful video compression standard and extended from H.264/MPEG-4 advanced video coding (AVC) for same level of video quality. However, H.265 improved better video quality for same bit rate. In video coding, motion estimation (ME) is determined the motion vector from adjacent frames. Various algorithms have been introduced by many researchers to accomplish low power oriented ME. However, low power oriented full search block based motion estimation (LP-FSBME) algorithm gives accurate results. Architecture of sum of absolute difference (SAD) is used an adder tree to accumulate the processing elements. Power efficient 16:2 adder compressors in SAD architecture reduce the power dissipation rather than convention adders in SAD architecture. The hardware implementation of proposed method is done in Xilinx Virtex 7 FPGA XC7VX1140T device with speed grade 1 in Xilinx software version 14.5 tool, developed in Verilog Hardware Description Language (Verilog-HDL), and simulated in ISE simulator for tennis, BQ terrace and Kimono videos with the resolution of 1080x720 pixels with 30fps.

scholarly journals A Motion Estimation based Algorithm for Encoding Time Reduction in HEVC

2022 ◽  
Vol 72 (1) ◽  
pp. 56-66
Author(s):  
S. Karthik Sairam ◽  
P. Muralidhar
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Video Compression ◽  
High Efficiency ◽  
Search Algorithm ◽  
Video Quality ◽  
Search Pattern ◽  
Absolute Difference ◽  
High Efficiency Video Coding ◽  
Search Patterns

High Efficiency Video Coding (HEVC) is a video compression standard that offers 50% more efficiency at the expense of high encoding time contrasted with the H.264 Advanced Video Coding (AVC) standard. The encoding time must be reduced to satisfy the needs of real-time applications. This paper has proposed the Multi- Level Resolution Vertical Subsampling (MLRVS) algorithm to reduce the encoding time. The vertical subsampling minimizes the number of Sum of Absolute Difference (SAD) computations during the motion estimation process. The complexity reduction algorithm is also used for fast coding the coefficients of the quantised block using a flag decision. Two distinct search patterns are suggested: New Cross Diamond Diamond (NCDD) and New Cross Diamond Hexagonal (NCDH) search patterns, which reduce the time needed to locate the motion vectors. In this paper, the MLRVS algorithm with NCDD and MLRVS algorithm with NCDH search patterns are simulated separately and analyzed. The results show that the encoding time of the encoder is decreased by 55% with MLRVS algorithm using NCDD search pattern and 56% with MLRVS using NCDH search pattern compared to HM16.5 with Test Zone (TZ) search algorithm. These results are achieved with a slight increase in bit rate and negligible deterioration in output video quality.

FPGA-Based ROI Encoding for HEVC Video Bitrate Reduction

2020 ◽  
Vol 29 (11) ◽  
pp. 2050182
Author(s):  
Zhilei Chai ◽  
Shen Li ◽  
Qunfang He ◽  
Mingsong Chen ◽  
Wenjie Chen
Keyword(s):  
Data Storage ◽  
Video Compression ◽  
High Efficiency ◽  
Video Quality ◽  
Region Of Interest ◽  
Absolute Difference ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Mapping Algorithm ◽  
Block Based

The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos ([Formula: see text]), and the bitrate is reduced by 10% on average with stable video quality.

Block-based motion estimation algorithms — a survey

2013 ◽  
Vol 21 (1) ◽  
Author(s):  
M. Jakubowski ◽  
G. Pastuszak
Keyword(s):  
Computational Complexity ◽  
Motion Estimation ◽  
Video Coding ◽  
Extensive Review ◽  
Matching Criterion ◽  
Estimation Algorithms ◽  
Standard Block ◽  
Block Based ◽  
Full Search

AbstractIn the multi-view video coding, both temporal and inter-view redundancies can be exploited by using standard block-based motion estimation (BBME) technique. In this paper, an extensive review of BBME algorithms proposed within the last three decades is presented. Algorithms are divided into five categories: 1) based on the search position number reduction; 2) multiresolution; 3) based on the simplification of matching criterion; 4) fast full search; 5) computation-aware. Algorithms are compared in terms of their efficiency and computational complexity.

scholarly journals Block Based Motion Estimation Algorithms: Analysis

2020 ◽  
Vol 14 ◽  
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
Video Processing ◽  
Search Algorithm ◽  
Video Sequences ◽  
Estimation Process ◽  
Estimation Algorithms ◽  
Block Based ◽  
Temporal Redundancy ◽  
Full Search

several video coding standards and techniques have been introduced for multimedia applications, particularly h.26x series for video processing. These standards employ motion estimation process in order to reduce the amount of data that is required to store or transmit the video. Motion estimation process is an inextricable part of the video coding as it removes the temporal redundancy between successive frames of video sequences. This paper is about these motion estimation algorithms, their search procedures, complexity, advantages, and limitations. A survey of motion estimation algorithms including full search algorithm, many fast search and fast full search block based algorithms has been presented. An evaluation of up to date motion estimation algorithms, based on a number of empirical results on several test video sequences, is presented as well.

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