Modeling Communication in Multi–Processor Systems–on–Chip Using Modular Connectors

2012 ◽  
pp. 219-240 ◽  
Author(s):  
Leonidas Tsiopoulos ◽  
Kaisa Sere ◽  
Juha Plosila
Keyword(s):  
Formal Methods ◽  
Concurrent Programming ◽  
Asynchronous Communication ◽  
New Approach ◽  
Action Systems ◽  
Modeling Methodology ◽  
Distributed Framework ◽  
Systems On Chip ◽  
On Chip

Formal methods of concurrent programming can be used to develop and verify complex Multi–Processor Systems–On–Chip in order to ensure that these systems satisfy their functional and communication requirements. The authors use the Action Systems formalism and show how asynchronous communication of Multi–Processor Systems–on–Chip can be modeled using generic connectors composed out of simple channel components. The paper proposes a new approach to modeling generic and hierarchical connectors for handling the complexity of on–chip communication and data flow. The authors’ goal is to avoid overloaded bus–based architectures and give a distributed framework. A case study presents the authors’ modeling methodology.

Modeling Communication in Multi–Processor Systems–on–Chip Using Modular Connectors

2010 ◽  
Vol 1 (2) ◽  
pp. 23-44 ◽  
Author(s):  
Leonidas Tsiopoulos ◽  
Kaisa Sere ◽  
Juha Plosila
Keyword(s):  
Formal Methods ◽  
Concurrent Programming ◽  
Asynchronous Communication ◽  
New Approach ◽  
Action Systems ◽  
Modeling Methodology ◽  
Distributed Framework ◽  
Systems On Chip ◽  
On Chip

Formal methods of concurrent programming can be used to develop and verify complex Multi–Processor Systems–On–Chip in order to ensure that these systems satisfy their functional and communication requirements. The authors use the Action Systems formalism and show how asynchronous communication of Multi–Processor Systems–on–Chip can be modeled using generic connectors composed out of simple channel components. The paper proposes a new approach to modeling generic and hierarchical connectors for handling the complexity of on–chip communication and data flow. The authors’ goal is to avoid overloaded bus–based architectures and give a distributed framework. A case study presents the authors’ modeling methodology.

scholarly journals The TaPaSCo Open-Source Toolflow

2021 ◽  
Author(s):  
Carsten Heinz ◽  
Jaco Hofmann ◽  
Jens Korinth ◽  
Lukas Sommer ◽  
Lukas Weber ◽  
...  
Keyword(s):  
Open Source ◽  
System Integration ◽  
Design Space Exploration ◽  
Systems On Chip ◽  
Spatially Distributed ◽  
On Chip ◽  
Many Core ◽  
Hardware Designs ◽  
Application Specific

AbstractThe integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.

A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs

2013 ◽  
Vol 4 (1) ◽  
pp. 22-41 ◽  
Author(s):  
Antonio Miele ◽  
Christian Pilato ◽  
Donatella Sciuto
Keyword(s):  
System Level ◽  
System Level Design ◽  
Simulation Environment ◽  
Processing Application ◽  
Systems On Chip ◽  
Simulation Based ◽  
Level Design ◽  
On Chip ◽  
Timing Models

The efficient analysis and exploration of mapping solutions of a parallel application on a heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) is usually a challenging task in system-level design, in particular when the architecture integrates hardware cores that may expose reconfigurable features. This paper proposes a system-level design framework based on SystemC simulations for fulfilling this task, featuring (i) an automated flow for the generation of timing models for the hardware cores starting from the application source code, (ii) an enhanced simulation environment for SystemC architectures enabling the specification and modification of mapping choices only by changing an XML descriptor, and (iii) a flexible controller of the simulation environment supporting the exploration of various mapping solutions featuring a customizable engine. The proposed framework has been validated with a case study considering an image processing application to show the possibility to automatically exploring alternative solutions onto a reconfigurable MPSoC platform.

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

2012 ◽  
pp. 263-277
Author(s):  
Sanna Määttä ◽  
Leandro Möller ◽  
Leandro Soares Indrusiak ◽  
Luciano Ost ◽  
Manfred Glesner ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Space Exploration ◽  
Network On Chip ◽  
Multiprocessor Systems ◽  
Trade Off ◽  
Successive Refinement ◽  
Systems On Chip ◽  
On Chip ◽  
Abstraction Levels

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

A Formal Language For Specifying Visual Interface Signifiers

2016 ◽  
Vol 60 (1) ◽  
pp. 1098-1102 ◽  
Author(s):  
Andrew J. Abbate ◽  
Ellen J. Bass
Keyword(s):  
Formal Methods ◽  
User Interfaces ◽  
Interface Design ◽  
Smart Phone ◽  
New Approach ◽  
Design Cycle ◽  
Limited Support ◽  
Visual Interface ◽  
Insight Into

User interfaces are often designed with signifiers that support end-users in understanding the function and meaning of device components. Formal methods have been successfully applied to support computational usability analyses early in the interface design cycle, without the need for a physical interface prototype. However limited support exists for applying formal methods to the analysis of signifiers. This paper presents the XML-based language of Browser-Integrated Guidance for Specifying Interface Signifiers (BIGSIS), a new approach that supports such an analysis. We employ BIGSIS-XML in a smart phone alarm clock case study to provide insight into the use of formal signifier specifications to inform the design of visual interface properties that operate as signifiers.

New approach to design for reusability of arithmetic cores in systems-on-chip

Integration ◽  
2004 ◽  
Vol 38 (2) ◽  
pp. 185-203
Author(s):  
Martin Margala ◽  
Hongfan Wang
Keyword(s):  
New Approach ◽  
Systems On Chip ◽  
On Chip

scholarly journals Formal Specification and Verification of Communication in Network-On-Chip: An Overview

2018 ◽  
Vol 6 (4) ◽  
pp. 15
Author(s):  
Fateh Boutekkouk
Keyword(s):  
Formal Methods ◽  
Formal Specification ◽  
Formal Analysis ◽  
Network On Chip ◽  
The Other ◽  
Communication Behavior ◽  
Systems On Chip ◽  
Formal Specification And Verification ◽  
Quantitative Properties ◽  
On Chip

Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits  especially scalability and communication performances. A NOC includes many applications that can execute concurrently. This situation may show some undesirable behaviors such as deadlock, livelock, starvation, etc. On the other hand, the application of formal methods to on-chip communication infrastructures has recieved more attention. Formal analysis of NOC communication will be very advantageous since it allows proving some theorems or interesting qualitative/quantitative properties on the communication behavior where simulation/emulation techniques can fail easily. In this paper we try to giva an overview of the most famous formal methods applied to the verification of communication inside NOCs.

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

2010 ◽  
Vol 1 (1) ◽  
pp. 86-101 ◽  
Author(s):  
Sanna Määttä ◽  
Leandro Möller ◽  
Leandro Soares Indrusiak ◽  
Luciano Ost ◽  
Manfred Glesner ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Network On Chip ◽  
Multiprocessor Systems ◽  
Single Application ◽  
Successive Refinement ◽  
Systems On Chip ◽  
On Chip ◽  
Abstraction Levels

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

Sign in / Sign up

Export Citation Format

Share Document