Research and Hardware Design of Scalable Dual-Field Montgomery Modular Inversion Algorithm

2011 ◽  
Vol 58-60 ◽  
pp. 1007-1012
Author(s):  
Lin Chen ◽  
Wan Zhong Sun ◽  
Xing Yuan Chen ◽  
Chao Zhou
Keyword(s):  
Elliptic Curve ◽  
Prime Number ◽  
Elliptic Curve Cryptography ◽  
Arithmetic Operation ◽  
Hardware Design ◽  
Operation Time ◽  
Hardware Architecture ◽  
Inversion Algorithm ◽  
Modular Inversion ◽  
Hardware Designs

The modular inversion is an essential and the most time consuming arithmetic operation in Elliptic Curve Cryptography (ECC). This paper presents an improved scalable dual-field Montgomery modular inversion algorithm which is based on Kaliski algorithm. It can support the prime number modular inversion algorithm and binary modular inversion algorithm. According to the algorithm, the hardware architecture is designed. The result of experimentation shows that the hardware design is superior to other hardware designs in operation time, circuit area and flexibility.

scholarly journals Scalable Normal Basis Arithmetic Unit for Elliptic Curve Cryptography

10.14311/688 ◽  
2005 ◽  
Vol 45 (2) ◽  
Author(s):  
J. Schmidt ◽  
M. Novotný
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Additional Data ◽  
Public Key Cryptography ◽  
Normal Basis ◽  
Public Key ◽  
Arithmetic Unit ◽  
Inversion Algorithm ◽  
Implementation Data ◽  
And Inversion

The design of a scalable arithmetic unit for operations over elements of GF(2m) represented in normal basis is presented. The unit is applicable in public-key cryptography. It comprises a pipelined Massey-Omura multiplier and a shifter. We equipped the multiplier with additional data paths to enable easy implementation of both multiplication and inversion in a single arithmetic unit. We discuss optimum design of the shifter with respect to the inversion algorithm and multiplier performance. The functionality of the multiplier/inverter has been tested by simulation and implemented in Xilinx Virtex FPGA.We present implementation data for various digit widths which exhibit a time minimum for digit width D = 15.

High-performance hardware architecture of elliptic curve cryptography processor over GF(2163)

2009 ◽  
Vol 10 (2) ◽  
pp. 301-310 ◽  
Author(s):  
Yong-ping Dan ◽  
Xue-cheng Zou ◽  
Zheng-lin Liu ◽  
Yu Han ◽  
Li-hua Yi
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Performance ◽  
Hardware Architecture
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