The Design and Verification of VGA Controller

2014 ◽  
Vol 981 ◽  
pp. 82-85
Author(s):  
Bin Yu ◽  
Yang Guang
Keyword(s):  
Hardware Implementation ◽  
Cordic Algorithm ◽  
Output Data ◽  
Simple Addition ◽  
Input And Output ◽  
Entire Structure ◽  
Hardware Implementations ◽  
Simulation Results ◽  
Sine And Cosine Functions ◽  
Cosine Functions

CORDIC Algorithm is widely applicable to the hardware implementation of DSP, and it attaches a great importance in many hardware implementations of DSP for a lot of arithmetic operations are simplified to simple addition operations and shifting operations. The FPGA implement of sine and cosine functions are achieved through CORDIC Algorithm in the paper, and the input and output data of the entire structure complies with IEEE754 standards. The basic theory of CORDIC Algorithm is introduced first in the paper, then the hardware iterative formula and the flow chart get out of basic formulas are given, and the structure of the design is introduced in detail, at last synthesis and simulation results are given.

The Implementation of Single Precision Sin&Cos Function on FPGA Based on the CORDIC Algorithm

2013 ◽  
Vol 380-384 ◽  
pp. 1812-1815
Author(s):  
Bin Yu ◽  
Yang Guang ◽  
Hai Huang
Keyword(s):  
Hardware Implementation ◽  
Cordic Algorithm ◽  
Single Precision ◽  
Output Data ◽  
Simple Addition ◽  
Input And Output ◽  
Entire Structure ◽  
Hardware Implementations ◽  
Sine And Cosine Functions ◽  
Cosine Functions

CORDIC Algorithm is widely applicable to the hardware implementation of DSP, and it attaches a great importance in many hardware implementations of DSP for a lot of arithmetic operations are simplified to simple addition operations and shifting operations. The FPGA implement of sine and cosine functions are achieved through CORDIC Algorithm in the paper, and the input and output data of the entire structure complies with IEEE754 standards. The basic theory of CORDIC Algorithm is introduced first in the paper, then the hardware iterative formula and the flow chart get out of basic formulas are given, and the structure of the design is introduced in detail, at last synthesis and simulation results are given.

The Nonlinearities of Memoryless Power Amplifier and Model of Predistorter

2014 ◽  
Vol 981 ◽  
pp. 40-45
Author(s):  
Huan Yang ◽  
Yuan Zhi He
Keyword(s):  
Power Amplifier ◽  
Mathematic Model ◽  
Polynomial Model ◽  
Least Square ◽  
Output Data ◽  
Input And Output ◽  
Adaptive Lms ◽  
Simulation Results

By analyzing the input and output data of memoryless power amplifier (PA), we construct the polynomial model and study the nonlinearities characteristics of it. Based on that the mathematic model of predistorter is gained, Least-square (LS) and adaptive LMS are used respectively to solve the question. Simulation results demonstrate predistortion can effectively correct the nonlinearities and both LS and LMS work well depending on different conditions.

Design of DDS Based on Improved CORDIC Algorithm

2012 ◽  
Vol 588-589 ◽  
pp. 727-730
Author(s):  
Zong Yao Liu ◽  
Wei Hua Zhu ◽  
Zhen Hua Qu
Keyword(s):  
Parallel Computing ◽  
High Precision ◽  
Hardware Implementation ◽  
Cordic Algorithm ◽  
Traditional Algorithm ◽  
Multi Level ◽  
Simulation Results ◽  
Computing Method ◽  
Computation Speed ◽  
Computing Speed

For the shortcomings that computation speed of the DDS decreases with iterations increasing in CORDIC algorithm., the traditional algorithm of multiple iterations is displaced by a point of decompose predict the direction of rotation and multi-level iterative parallel computing method in this paper. The function simulation results show that the improved algorithm enhance the computation speed and maintain data high precision. This design has high computing speed, high precision and simple hardware implementation etc.

ARCTANGENT ARCHITECTURE FOR HIGH SPEED AND HIGH PRECISION DATA

2011 ◽  
Vol 20 (07) ◽  
pp. 1243-1259 ◽  
Author(s):  
SAMIR TAGZOUT ◽  
ADEL BELOUCHRANI
Keyword(s):  
High Precision ◽  
High Speed ◽  
Vlsi Design ◽  
Output Data ◽  
Precision Data ◽  
Input And Output ◽  
Hardware Implementations ◽  
High Precision Data ◽  
Logical Design ◽  
Arctangent Function

The Arctangent function is used in several signal processing applications and it is widely needed for hardware implementations. However, it often constitutes the performance bottleneck because of its inaccuracy and/or its poor performances. We present a generic VLSI design to respond to some applications' need of fast Arctangent functions handling high precision data. The method presented here contrasts with the usual Look Up table based solutions which allow the output customization but limit the precision of the corresponding tangent input. Detailed logical design and FPGA implementation results are provided to show our solution as the best candidate to comply with fast execution as well as high precision for both input and output data.

Some Mellin-type Definite Integrals Involving Sine and Cosine Functions

2019 ◽  
Vol 10 (1) ◽  
pp. 222-237
Author(s):  
M. I. Qureshi ◽  
Kaleem A. Quraishi ◽  
Dilshad Ahamad
Keyword(s):  
Definite Integrals ◽  
Sine And Cosine Functions ◽  
Cosine Functions

scholarly journals A Profit Distribution Model of Reverse Logistics Based on Fuzzy DEA Efficiency—Modified Shapley Value

2021 ◽  
Vol 13 (13) ◽  
pp. 7354
Author(s):  
Jiekun Song ◽  
Xiaoping Ma ◽  
Rui Chen
Keyword(s):  
Shapley Value ◽  
Reverse Logistics ◽  
Service Providers ◽  
Third Party ◽  
Output Data ◽  
Profit Distribution ◽  
Logistics Service ◽  
Input And Output ◽  
Value Model ◽  
Fuzzy Dea

Reverse logistics is an important way to realize sustainable production and consumption. With the emergence of professional third-party reverse logistics service providers, the outsourcing model has become the main mode of reverse logistics. Whether the distribution of cooperative profit among multiple participants is fair or not determines the quality of the implementation of the outsourcing mode. The traditional Shapley value model is often used to distribute cooperative profit. Since its distribution basis is the marginal profit contribution of each member enterprise to different alliances, it is necessary to estimate the profit of each alliance. However, it is difficult to ensure the accuracy of this estimation, which makes the distribution lack of objectivity. Once the actual profit share deviates from the expectation of member enterprise, the sustainability of the reverse logistics alliance will be affected. This study considers the marginal efficiency contribution of each member enterprise to the alliance and applies it to replace the marginal profit contribution. As the input and output data of reverse logistics cannot be accurately separated from those of the whole enterprise, they are often uncertain. In this paper, we assume that each member enterprise’s input and output data are fuzzy numbers and construct an efficiency measurement model based on fuzzy DEA. Then, we define the characteristic function of alliance and propose a modified Shapley value model to fairly distribute cooperative profit. Finally, an example comprising of two manufacturing enterprises, one sales enterprise, and one third-party reverse logistics service provider is put forward to verify the model’s feasibility and effectiveness. This paper provides a reference for the profit distribution of the reverse logistics.

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

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