The effect of underfill on thermal stresses on logic ASIC and its electrical performance

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Babak Talebanpour ◽  
Doug Link
Keyword(s):  
Frequency Shift ◽  
Flip Chip ◽  
Thermal Stresses ◽  
Electrical Performance ◽  
Shear Stresses ◽  
Normal Stresses ◽  
Clock Frequency ◽  
Chip Technology ◽  
Solder Bumps ◽  
Solder Reflow

Flip chip technology is widely used today to support the demand for high interconnect density of modern microelectronic circuits. Conventionally, solder bumps have provided the electrical and mechanical connection between the chip and the substrate. The solder bumps are prone to fatigue and failure especially in large chips and/or mobile devices. Conventional underfilling process which consists of flowing an epoxy under the chip and curing it after the flip chip connections are made mechanically supports the assembly, significantly reducing the shear stresses on the bumps and minimizing the chip warpage due to thermal stresses. However, underfill also has side effects. The flow of underfill depends on a lot of parameters usually can be incomplete or containing a lot of voids, inconsistent underfill results in unpredictable overall durability or manufacturing survivability. Furthermore, underfilling introduces certain components of stress, this form of stress can have adverse effect on the electrical performance of the die if it occurs close to stress sensitive parts. In this study, the effect of underfilling and its quality on the clock frequency shift of a DSP (Digital Signal Processor) chip used by Starkey Hearing Technologies is investigated. Clock frequency measurements after a solder reflow process has been compared for different underfill materials, and underfill quality. Finite element analysis was implemented to assess the stress transferred to the clock circuit on the die and examine how existence of underfill, bump height, location of bumps, and underfill voids affect the stress. The following results have been concluded based on the work presented in this paper:The conventional underfilling process for dies with very small standoff heights can be very in consistent, strongly depending on the gap uniformity, flex traces, cleanliness of the package after solder reflow, etc. large percentage of delamination and voids can occur. The voids and delamination can cause solder extrusion as well as inconsistent stress distribution on the die.Although underfilling causes large normal stresses on the die, it reduces the effective stress on the die which can translate to less warpage and the problems associated with it.The height of the bumps does not strongly affect the amount of stress build up on the die if it does not compromise a uniform underfill.Relocation of the bumps away from the clock circuit significantly reduces the stress on the clock, and it has been shown to minimize the clock shift in practice. A minimum amount of distance between the clock circuit and solder bumps should be considered when DSP layout are designed.If the clock circuit surface is not in contact with the underfill, normal stresses will not be transferred to the clock circuit minimizing the clock frequency shift. The best approach to implement this method is wafer-level underfill technique. The underfill will be applied at the wafer fab and precision lasers can cut the underfill laminate at desired locations. This process can guarantee support for the die by a uniform underfill, while stress sensitive parts will be protected against unwanted thermal stresses.

Molding Recipe Study for MUF Solder Crack Improvement

2018 ◽  
Vol 2018 (1) ◽  
pp. 000121-000124
Author(s):  
Scott Chen ◽  
Leander Liang ◽  
Pallas Hsu ◽  
Tim Tsai ◽  
Mason Liang ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Flow Simulation ◽  
Test Vehicle ◽  
Chip Technology ◽  
Solder Bumps ◽  
Capillary Underfill ◽  
Mold Flow ◽  
Profile Reduction ◽  
Transfer Pressure

Abstract In recent years, flip chip technology becomes more and more important with benefits of thin package profile, reduction of package outline, and excellent electrical and thermal performance by connection of copper pillar bumps (CuP) or C4 solder bumps. In order to fill the die gap to prevent voids problem, two encapsulated solutions could be applied: capillary underfill (CUF) and molded underfill (MUF). In general comparison, CUF means to dispense underfill first to fill in die gap then proceed over-molding afterward; and MUF is directly fill under and above die by mold compound. The advantages of MUF solution are low cost and high throughput, however, it will suffer other assembly issues such as solder extrusion and solder crack, and might result in potential function failure. To form these kinds of defects, we suspected that solder will plastically deform under thermal stress treatment, which comes from unbalance mold transfer pressure and material expansion stress during thermal process. In this article, we have tried to investigate the mechanism of solder crack through molding recipe DOE (Design of Experiment) and mold flow simulation. The test vehicle is 12 × 12 mm2 FCCSP, with 6 × 5 mm2 die size. The bump type is copper pillar bump and pitch/size are 126 um and 35 × 60 um2, respectively. The molding recipe has been evaluated by cross section, and it revealed that molding transfer time and molding temperature are directions toward improvement of solder crack issue.

Bump Electromigration and Back End Design Rules

2007 ◽  
Author(s):  
Vishal Nagaraj ◽  
Saket Karajgikar ◽  
Dereje Agonafer ◽  
Senol Pekin
Keyword(s):  
Flip Chip ◽  
Heat Dissipation ◽  
High Current Density ◽  
Electrical Performance ◽  
High Current ◽  
Current Crowding ◽  
Element Analysis ◽  
Chip Technology ◽  
Flip Chip Packaging ◽  
Current Densities

As there is continuous demand for miniaturization of electronic devices, flip chip technology is predominantly used for high density packaging. The technology offers several advantages like excellent electrical performance and better heat dissipation ability. Original invention of flip chip packaging utilized ceramic substrates and high lead bumps. Low cost commercialization of this packaging technology, however, required organic laminate substrates coupled with SnPb eutectic bumped interconnects on the die side. While organic laminate flip chip packaging may be a good option for many low power applications, current carrying capability of the eutectic bumped interconnect causes a catastrophic failure mechanism called electromigration. Previously, researchers have identified and addressed few issues regarding electromigration. Electomigration leads to the formation of metal voids in the conductors which eventually increases the resistance drop across the conductor causing electrical opens. Electromigration is very significant at high current densities. Temperature is the other parameter of concern for electromigration. High current density causes temperature to rise due to Joule heating, there by reducing the life of package. In order to determine the factors responsible for high current densities, we formed a full factorial design of experiments (DOE) that contained parameters such as passivation opening, UBM size, UBM thickness and trace width. Finite Element Analysis (FEA) was performed in order to study the effect of above parameters on current crowding and temperature in the bumped interconnects. Based on the results, hierarchy of the most important parameters to be considered while selecting the appropriate flip chip technology is proposed.

Measurement and Simulation of Moisture Induced Die Stresses in Flip Chip on Laminate Assemblies

2015 ◽  
Author(s):  
Quang Nguyen ◽  
Jordan C. Roberts ◽  
Jeffrey C. Suhling ◽  
Richard C. Jaeger ◽  
Pradeep Lall
Keyword(s):  
Flip Chip ◽  
Moisture Absorption ◽  
Moisture Diffusion ◽  
Shear Stresses ◽  
Experimental Measurements ◽  
Normal Stresses ◽  
Long Term Storage ◽  
Stress Changes ◽  
Term Storage

In this work, an investigation has been performed on hygrothermally induced die stresses in flip chip assemblies caused by moisture absorption by the underfill encapsulant. Silicon test chips were first applied to perform a variety of measurements of moisture and thermally induced die stresses in flip chip on laminate assemblies. The sample die stresses were first measured after underfill encapsulation and cure, and then subsequently after long term storage (10 years) at room temperature and ambient humidity. The assemblies were then exposed to and 85 °C and 85% RH high humidity harsh environment for various durations, and the die stresses were evaluated as a function of the exposure time. Finally, reversibility tests were conducted to see whether the effects of moisture uptake were permanent. After long term storage, the experimental measurements showed that the normal stresses in the flip chip die relaxed significantly, while the shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposure had strong effects, generating tensile die normal stress changes of up to 30 MPa in the flip chip assemblies. Thus, the initial compressive die normal stresses due to flip chip assembly were found to relax significantly during the moisture exposure. Upon fully redrying, it was observed that the moisture-induced stress changes were fully recovered. The results of the experimental measurements were subsequently correlated with predictions from finite element numerical simulations. When performing moisture diffusion modeling, the conventional method is to use a thermal analogy based on the similarity of governing equations of heat transfer and moisture diffusion. However, this method has some drawbacks including giving incorrect results when dealing with time- and temperature-dependent problems or discontinuities in the moisture concentrations at material boundaries. In this study, we have used a new feature in ANSYS v14 to perform coupled multi-physics simulations of the moisture diffusion process without the aforementioned limitations. The simulation results were found to show strong correlations with experimental measurements.

A Model for Underfill Viscous Flow Considering the Resistance Induced by Solder Bumps

2004 ◽  
Vol 126 (2) ◽  
pp. 186-194 ◽  
Author(s):  
Chyi-Lang Lai ◽  
Wen-Bin Young
Keyword(s):  
Flip Chip ◽  
External Pressure ◽  
Good Prediction ◽  
Parallel Plates ◽  
Rectangular Array ◽  
Chip Technology ◽  
Solder Bumps ◽  
Proposed Model ◽  
Filling Time ◽  
Underfill Flow

During the underfill process, polymers driven by either capillary force or external pressure are filled at a low speed between the chip and substrate. Current methods treated the flow in the chip cavity as a laminar flow between parallel plates, which ignored the resistance induced by the solder bumps or other obstructions. In this study, the filling flow between solder bumps was simulated by a flow through a porous media. By using the superposition of flows through parallel plates and series of rectangular ducts, permeability of the underfill flow was fully characterized by the geometric arrangement of solder bumps and flat chips. The flow resistances caused by adjacent bumps were represented in its permeability. The model proposed in this study could provide a numerical approach to approximate and simulate the undefill process for flip-chip technology. Although the proposed model is applicable for any geometric arrangement of solder bumps, rectangular-array of solder bumps layout was used first for comparison with experimental results of other article. Comparisons of the flow-front shapes and filling time with the experimental data indicated that the flow simulation obtained from the proposed model gave a good prediction for the underfill flow.

The Study on The Under Bump Metallurgy (Ubm) and 63SN-37PB Solder Bumps Interface for Flip Chip Interconnection

1998 ◽  
Vol 515 ◽  
Author(s):  
Se-Young Jang ◽  
Kyung-Wook Paik
Keyword(s):  
Shear Strength ◽  
Direct Contact ◽  
Flip Chip ◽  
Organic Substrates ◽  
Adhesion Properties ◽  
Ball Shear ◽  
Solder Bumps ◽  
Diffusion Barrier Layer ◽  
Solder Reflow ◽  
Ball Shear Strength

ABSTRACTIn the flip chip interconnection on organic substrates using eutectic Pb/Sn solder bumps, highly reliable Under Bump Metallurgy (UBM) is required to maintain adhesion and solder wettability. Various UBM systems such as l.tm Al/0.2 μm Ti/5 μm Cu, l μm A1/0.2 μm Ti/l μm Cu, 1 μm A1/0.2 μm Ni/1 μm Cu and 1 μm At/10.2μm Pd/l μm Cu, laid under eutectic Pb/Sn solder of low melting point, were investigated with regard to their interfacial reactions and adhesion properties. The effects of numbers of solder reflow and aging time on the growth of intermetallic compounds (IMC) and on the solder ball shear strength were investigated. Good ball shear strength was obtained with 1 μm AI/0.2μm Ti/5μm Cu and 1 μm Al/0.2 μm Ni/l μm Cu even after 4 solder reflows or 7 day aging at 150°C. In contrast, l μm Al/0.2 μm Ti/l μm Cu and l μm A1/0.21μm Pd/μm Cu shows poor ball shear strength. The decrease of the shear strength was mainly due to the direct contact between solder and nonwettable metal such as Ti and Al resulting in a delamination. Thin 1 μm Cu and 0.2 μm Pd diffusion barrier layer were completely consumed by Cu-Sn and Pd-Sn reaction.

Thermal Control of Interfaces for Microelectronic Packaging

1998 ◽  
Vol 515 ◽  
Author(s):  
E. E. Marotta ◽  
B. Hana
Keyword(s):  
Thermal Performance ◽  
Flip Chip ◽  
Printed Circuit Boards ◽  
Thermal Stresses ◽  
Experimental Studies ◽  
Thermal Control ◽  
Thermal Contact Conductance ◽  
Microelectronic Packaging ◽  
Chip Technology ◽  
Operating Temperatures

ABSTRACTThe continuous miniaturization of electronic devices places an ever-increasing importance on the thermal management of electronic systems and its subcomponents. The increased power densities and heat generation, due to the miniaturization of the device line features, may lead to higher operating temperatures and greater warpage between the silicon device and its organic carrier. The higher operating temperature may result from the degradation of the overall thermal performance. These additive effects will also lead to an increasing number of thermally induced failures, which will be further magnified when future microelectronic packaging incorporates flip-chip technology.The higher operating temperatures within microelectronic systems result from inadequate dissipation of the heat generated, while the warpage effect is caused by the mismatch between the thermal coefficients of expansion (ICE) induced by thermal stresses. Often these high temperatures result from the thermal resistance between subcomponents, such as between the contacting surfaces of laminated printed circuit boards, device/epoxy cement and heat spreader (i.e., finned heat sink or heat pipe), and any other metallic or non-metallic interstitial material employed between contacting interfaces.Published experimental data of potential coatings, adhesives, and elastomeric gaskets is presented that can improve the thermal contact conductance of contacting surfaces within microelectronic systems. In addition, recommendations for future analytical and experimental studies of the mnechanistic principles, which control thermal performance of interstitial materials, are discussed for non-uniform pressure distribution.

Prediction of Electromigration Critical Current Density in Passivated Arbitrary-Configuration Interconnect

2019 ◽  
Vol 141 (2) ◽  
Author(s):  
Yasuhiro Kimura ◽  
Masumi Saka
Keyword(s):  
Critical Current Density ◽  
Critical Current ◽  
Current Density ◽  
Flip Chip ◽  
Electrical Potential ◽  
Atomic Density ◽  
Configuration Model ◽  
Chip Technology ◽  
Arbitrary Configuration ◽  
Solder Bumps

A critical current density, a criterion of electromigration (EM) resistance in interconnects, above which EM damages initiate has been studied to minimize EM damages of interconnects. In general, the assessment of a critical current density is confined to straight interconnect called as Blech specimen, although the critical current density is sensitive to structural characteristic. This work proposes a procedure of predicting a critical current density for any arbitrary-configuration interconnect by using the analogy between atomic density and electrical potential. In the models of straight and barrel interconnects as the typical solder bumps in modern flip-chip technology, the critical current density is predicted through calculating electrical potential by proposed formulation and simulation based on the finite element analysis (FEA). The critical current density for straight interconnect obtained by experiment leads to numerically calculate the critical electrical potential, which is independent of interconnect configuration. The critical potential corresponds to the critical atomic density, below which the accumulation of atoms allows. The calculated critical electrical potential determines a critical current density for arbitrary-configuration interconnect including current crowding effect. This finding can predict a critical current density for actual arbitrary-configuration model and provide an insight for the applying to the packaging design such as ball grid array and C4 flip-chip solder bumps.

Cu Pillar Bump FCBGA Package Design and Reliability Assessments

2008 ◽  
Author(s):  
Nicholas Kao ◽  
Yen-Chang Hu ◽  
Yuan-Lin Tseng ◽  
Eason Chen ◽  
Jeng-Yuan Lai ◽  
...  
Keyword(s):  
Stress Distribution ◽  
High Performance ◽  
Flip Chip ◽  
Spherical Geometry ◽  
Electrical Performance ◽  
Design Factor ◽  
Cu Pillar ◽  
Chip Technology ◽  
Cu Pillar Bump ◽  
Low K

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more Input/Output (I/O) and better electrical characteristics under same package form factor. Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pin accommodation and high transmission speed. However, the flip chip technology is encountering its structure limitation as the bump pitch is getting smaller and smaller because the spherical geometry bump shape is to limit the fine bump pitch arrangement and it’s also difficult to fill by underfill between narrow gaps. As this demand, a new fine bump pitch technology is developed as “Cu pillar bump” with the structure of Cu post and solder tip. The Cu pillar bump is plating process manufactured structure and composes with copper cylinder (Cu post) and mushroom shape solder cap (Solder tip). The geometry of Cu pillar bump not only provides a finer bump pitch, but also enhances the thermal performances due to the higher conductivity than conventional solder material. This paper mainly characterized the Cu pillar bump structure stress performances of FCBGA package to prevent reliability failures by finite element models. First, the bump stress and Cu/low-k stress of Cu pillar bump were studied to compare with conventional bump structure. The purpose is to investigate the potential reliability risk of Cu pillar bump structure. Secondly, the bump stress and Cu/low-k stress distribution were evaluated for different Polyimide (PI) layer, Under Bump Metallization (UBM) size and solder mask opening (SMO) size. This study can show the stress contribution of each design factor. Thirdly, a matrix which combination UBM size, Cu post thickness, SMO size, PI opening and PI thickness were studied to observe the stress distribution. Finally, the stress simulation results were experimentally validated by reliability tests.

Development of Lead Free Plating Chemical for Various Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000944-000967
Author(s):  
Takeshi Hatta ◽  
Atsushi Ishikawa ◽  
Takuma Katase ◽  
Akihiro Masuda
Keyword(s):  
Chemical Stability ◽  
High Speed ◽  
Flip Chip ◽  
New Technologies ◽  
High Reliability ◽  
Lead Free ◽  
Current Status ◽  
Chip Technology ◽  
Solder Bumps ◽  
Pure Sn

Flip chip connection has been applied to a lot of applications to shorten the connection length for high performance. Solder bumping is one of the key technologies for flip chip connection, and its quality strongly brings large impact on the reliability after packaging. Electroplating is one of the methods to form solder bumps. And Sn-Ag is considered as the first candidate of lead free alloy for electroplating method. We have released Sn-Ag plating chemical and it has been used by many customers in the world. In the future, flip chip technology will progress to further miniaturization and high integration with the new technologies such as Cu pillar and Through Silicon Via (TSV). At that time, further variations of alloys are necessary for electroplating method to meet various requirements. Even for Sn-Ag plating chemical, higher plating rate is required to improve productivity in mass production. In this time, we have developed new Sn-Ag high speed plating chemical based on our conventional technology. Furthermore, we have succeeded to develop Pure Sn and Sn-Cu chemicals for bumping method to meet customer's requirement. Sn-Cu is considered as a good candidate for bumping alloy to achieve high reliability, but the chemical stability is not so good. Therefore, we successfully modified the Sn-Cu chemical and extended chemical stability. We will update our current status about high speed Sn-Ag plating chemical and other chemicals like Sn-Cu and pure Sn in this time. By using these binary alloy chemicals, we are able to produce Sn-Ag-Cu solder bumps by stacking Sn-Ag and Sn-Cu. And it can bring further variation for bumping alloys.

Adapted assembly processes for flip-chip technology with solder bumps of 50 µm or 40 µm diameter

2010 ◽  
Author(s):  
Rainer Dohle ◽  
Florian Schussler ◽  
Thomas Friedrich ◽  
Jorg Gossler ◽  
Thomas Oppert ◽  
...  
Keyword(s):  
Flip Chip ◽  
Chip Technology ◽  
Solder Bumps
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