Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection

2019 ◽  
Vol 2019 (1) ◽  
pp. 000216-000222
Author(s):  
Chun-Hsien Chien ◽  
Chien-Chou Chen ◽  
Wen-Liang Yeh ◽  
Wei-Ti Lin ◽  
Cheng-Hui Wu ◽  
...  
Keyword(s):  
Stress Test ◽  
Dielectric Materials ◽  
Circuit Board ◽  
Strip Line ◽  
Organic Substrates ◽  
Next Generation ◽  
Glass Panel ◽  
Process Technology ◽  
Fine Line ◽  
Ic Foundry

Abstract In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (< 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.

Result of high accelerated stress test of organic substrates made by integrated dry process

2018 ◽  
Vol 2018 (1) ◽  
pp. 000153-000160
Author(s):  
Tomoyuki Habu ◽  
Shinichi Endo ◽  
Shintaro Yabu
Keyword(s):  
Printed Circuit Board ◽  
New Technology ◽  
Stress Test ◽  
Power Saving ◽  
Circuit Board ◽  
Organic Substrates ◽  
Dry Process ◽  
Seed Technology ◽  
Interfacial Surface ◽  
Accelerated Stress Test

Abstract The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process “Integrated dry process” using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove a smear remaining behind in the via bottom by Photodesmear. Furthermore, we improved adhesion between copper metal and epoxy resin in a sputtering seed together. We made the large experimental tool that Photodesmear could process an actually size of the print circuit board by static irradiation. And we proved that handling of panel size was technically possible. The connection reliability of the contact via is evaluated after electric copper plating by quick via peel examination. A cross section of the vias was made and, the residual smear removal properties of wet desmear processing and the Photodesmear processing were compared with the residual smear and the thin oxidation layer by observation of the connection interface. The interfacial surface state after the desmear processing was analyzed in X-ray probe analyzer. We produced the test vehicle using Photodesmear technology and a sputtering seed technology. I compared it with the same pattern sample produced by a process conventionally. In this paper, we report the result of the high accelerated temperature and humidity stress test.

Development of High Permeability Core Materials for Embeddable Inductors in Flexible Organic Substrates

2003 ◽  
Vol 769 ◽  
Author(s):  
C. K. Liu ◽  
P. L. Cheng ◽  
S. Y. Y. Leung ◽  
T. W. Law ◽  
D. C. C. Lam
Keyword(s):  
Low Temperature ◽  
Sol Gel ◽  
Circuit Board ◽  
Organic Substrates ◽  
Circuit Boards ◽  
High Permeability ◽  
Electrical Measurements ◽  
Different Temperatures ◽  
Spiral Inductors ◽  
Ceramic Tape

AbstractCapacitors, resistors and inductors are surface mounted components on circuit boards, which occupy up to 70% of the circuit board area. For selected applications, these passives are packaged inside green ceramic tape substrates and sintered at temperatures over 700°C in a co-fired process. These high temperature processes are incompatible with organic substrates, and low temperature processes are needed if passives are to be embedded into organic substrates. A new high permeability dual-phase Nickel Zinc Ferrite (DP NZF) core fabricated using a low temperature sol-gel route was developed for use in embedded inductors in organic substrates. Crystalline NZF powder was added to the sol-gel precursor of NZF. The solution was deposited onto the substrates as thin films and heat-treated at different temperatures. The changes in the microstructures were characterized using XRD and SEM. Results showed that addition of NZF powder induced low temperature transformation of the sol-gel NZF phase to high permeability phase at 250°C, which is approximately 350°C lower than transformation temperature for pure NZF sol gel films. Electrical measurements of DP NZF cored two-layered spiral inductors indicated that the inductance increased by three times compared to inductors without the DP NZF cores. From microstructural observations, the increase is correlated with the changes in microstructural connectivity of the powder phase.

Reliability Performance of 1200 V and 1700 V 4H-SiC DMOSFETs for Next Generation Power Conversion Applications

2014 ◽  
Vol 778-780 ◽  
pp. 967-970 ◽  
Author(s):  
Donald A. Gajewski ◽  
Sei Hyung Ryu ◽  
Mrinal Das ◽  
Brett Hull ◽  
Jonathan Young ◽  
...  
Keyword(s):  
Wide Bandgap ◽  
Large Sample Size ◽  
Next Generation ◽  
Process Technology ◽  
Power Switching ◽  
Comprehensive Reliability ◽  
Reliability Performance ◽  
Acceptance Tests ◽  
Frequency Power

We present new reliability results on the Cree, Inc., 4H-SiC, DMOSFET devices. The Cree DMOSFETs were developed to meet the demand of next-generation, high-frequency power switching applications, such as: dc-ac inversion, dc-dc conversion, and ac-dc rectification, with continually improving energy efficiency. The Cree Generation 2 DMOSFET process technology is now commercially available with 1200 V and 1700 V ratings. We have performed intrinsic reliability studies to ensure excellent wear-out performance and long field lifetime of the products. We have also performed large sample size qualification reliability acceptance tests to ensure the quality of the manufacturing and packaging processes. These comprehensive reliability studies establish new benchmarks for wide bandgap transistors and demonstrate that Crees MOSFETs meet or exceed all industrial reliability requirements. This achievement facilitates broad market adoption of this disruptive power switch technology.

Electromigration in Power Devices

2020 ◽  
Vol 2020 (1) ◽  
pp. 000078-000084
Author(s):  
Hao Zhuang ◽  
Robert Bauer ◽  
Markus Dinkel
Keyword(s):  
Current Density ◽  
Flip Chip ◽  
Semiconductor Industry ◽  
Stress Test ◽  
Test System ◽  
Circuit Board ◽  
Power Device ◽  
Current Direction ◽  
Power Devices ◽  
Maximum Current

Abstract In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

Advanced Low Df Dry film Build-up Material on Glass panel for 5G application

2020 ◽  
Vol 2020 (1) ◽  
pp. 000201-000205
Author(s):  
Takenori Kakutani ◽  
Zhong Guan ◽  
Yuya Suzuki ◽  
Muhammad Ali ◽  
Serhat Erdogan ◽  
...  
Keyword(s):  
High Frequency ◽  
Transmission Loss ◽  
Core Material ◽  
Wave Band ◽  
Organic Substrates ◽  
Frequency Filter ◽  
Transmission Characteristics ◽  
Glass Panel ◽  
Low Loss ◽  
Dry Film

Abstract This paper describes the demonstration of a low loss substrate (laminated glass) for high-frequency transmission using a dry film build-up material with low loss tangent (Df). This paper also evaluates filter characteristics and dielectric characteristics of the substrate in the mm-Wave band. The advanced low loss dry film build-up material was newly developed, and applicable to high frequency transmission. This material has a Df of 0.0025 at 10 GHz and also exhibits excellent adhesion and electrical reliability required for advanced dielectric materials. In addition, glass was used as a core material in this paper because of its excellent signal transmission characteristics compared to silicon wafers or organic substrates. To demonstrate the benefit of low loss materials for high frequency transmission, passive components for high frequency filter substrates were fabricated using - 6-inch square thin (0.2mm) glass panel with various build-up materials (Material A with a Df of 0.0025, and Material B with a Df 0.0042 at 10 GHz) laminated. Copper wiring patterns on the dielectric layers were fabricated by a semi-additive process (SAP). Circuit patterns with low pass filters and band pass filters were also fabricated. First, transmission characteristics and characteristic impedances were measured to check the electrical performance. The measured lowest transmission loss of < 1.43 dB at 39 GHz were achieved when Material A was applied as the build-up material. Second, biased-highly accelerated stress test (bHAST) was conducted to evaluate the reliability performance of the substrates with two build-up materials, Material A and a conventional material. The test condition was based on the JEDEC level 2 standard. The substrate with Material A retained good insulation properties over 300 hours of bHAST treatment, demonstrating its excellent insulating performance. In summary, Material A has been shown in this paper to exhibit reduced transmission loss in high-frequency filter substrates at millimeter wave frequencies.

Novel Formaldehyde-Free Electroless Copper for Plating on Next Generation Substrates

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000977-001004
Author(s):  
Christian Wendeln ◽  
Edith Steinhäuser ◽  
Lutz Stamp ◽  
Bexy Dosse-Gomez ◽  
Elisa Langhammer ◽  
...  
Keyword(s):  
Printed Circuit Boards ◽  
Dielectric Materials ◽  
Reducing Agent ◽  
Operating Conditions ◽  
Copper Layer ◽  
Complexing Agents ◽  
Next Generation ◽  
Production Scale ◽  
Diverse Range ◽  
Electroless Copper

The deposition of electroless Copper on dielectric substrates and the subsequent electrolytic build-up of a thicker Copper layer are widely used steps within the production of modern Printed Circuit Boards (PCB), and while there have been numerous developments within PCB production, the current manufacturing technologies continue to be reliant on the autocatalytic deposition of Copper from a solution containing formaldehyde as the reducing agent, even though the chemistry is known to pose a risk to human health. Further, as the high volatility of formaldehyde generally increases the exposure to the hazard, it is understood that critical air concentrations can easily be exceeded. With this in mind it is clear that the development of environmental and user friendly electroless Copper baths has become a subject of importance. Nevertheless, the introduction of “green” plating chemistry into the market remains a challenge due to high industrial standards in terms of performance and cost-efficiency, which have been established by the conventional plating products and limit their replacement. In the case of the electroless Copper baths, formaldehyde-free alternatives have to show excellent substrate coverage with metal, provide coatings with high conductivity and uniformity and should lead to very good reliability results. Moreover, the solution, and final Copper layer have to function with the diverse range of dielectric materials that are currently employed. Due to application needs, there has been a shift within PCB design towards the use of very smooth substrate materials with low coefficients of thermal expansion. Such materials offer the opportunity for further miniaturization of circuits and are optimal for adoption within packaged die components (IC substrates). However, smooth substrate topographies typically lead to a limited adhesion of the electroless Copper layer, and increases the risk of delamination or blister formation. To prevent this, the properties of the metal film itself, as well as the chemical properties of the Copper bath, from which it is deposited, are critical, with a key factor being that the deposited layer is generated under internal tensile stress, as this has been shown to be of importance in reducing blister occurrence. While formaldehyde based plating solutions have been modified to satisfy this requirement through the adoption of additives and organic substances, there is still very little experience available regarding chemical approaches utilizing other reducing agents. Changing the reducing agent generally requires a complete redesign of the electroless system, including careful selection of the complexing agents and additives, readjustment of the chemical concentrations and optimization of the baths physical operating conditions. In this work we describe a new type of formaldehyde-free electroless Copper solution suitable for a broad set of applications and materials, and specifically the processing of next-generation substrates. This new plating solution has been successfully applied in both laboratory and production-scale environments, with its performance being evaluated and benchmarked against an existing formaldehyde-containing reference. The obtained metal layer has been characterized through a number of analytical techniques, including microscopy, XRF, SEM, adhesion tests as well as non-blister performance. Based on the data obtained we believe that the newly developed solution utilizing a non-formaldehyde reducing agent provides a suitable technology for PCB production without a loss of process performance, and thus provide a sustainable “green” alternative to the industry.

Low Temperature Curing - Aqueous Base Developable Photoimageable Dielectric for WLP (Wafer Level Packaging)

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000986-001015
Author(s):  
Eric Huenger ◽  
Joe Lachowski ◽  
Greg Prokopowicz ◽  
Ray Thibault ◽  
Michael Gallagher ◽  
...  
Keyword(s):  
Low Temperature ◽  
Dielectric Material ◽  
Broad Band ◽  
Dielectric Materials ◽  
Next Generation ◽  
Wafer Level ◽  
Moore’S Law ◽  
Moore's Law ◽  
3D Chip Stacking ◽  
The Impact

As advanced packaging application space evolves and continues to deviate from the conventional shrinkage pathway predicted by Moore's law, material suppliers need to continue to work with OEMs, OSATs and Foundries to identify specific opportunities. One such opportunity continues to present itself in developing new materials to support new platforms for next generation products to support 3D chip stacking and TSV applications. The newer material sets can be established to meet more challenging design requirements associated with the demands, presented by the application from both a physical/lithographical processing and design perspective. Next generation packages requires the development of new dielectric materials that can support both the physical demands of 3D chip stacking and TSV package design aspects while maintaining strengths of the existing material platform. While vertical integration necessitates the use of thinned substrates and its associated integration challenges, there is a continuing need to support horizontal shrinkage typical of the Moore's Law, which pushes the lithography envelope requiring finer pitch and smaller feature resolution capability. This presentation identifies the strategy we have taken and highlights approach taking in the development of low temperature curable photoimageable dielectric materials with enhanced lithographic performance. We will discuss the methodology used to create benzocyclobutene based dielectric material curable at 180 °C and show how lithographic performance can be tuned to allow sub 5 micron via using broad band illumination. Finally we will review the impact of low temperature processing on the mechanical, thermal and electrical properties of this novel photoimageable dielectric material.

Perspectives and challenges in multilayer ceramic capacitors for next generation electronics

2019 ◽  
Vol 7 (32) ◽  
pp. 9782-9802 ◽  
Author(s):  
Kootak Hong ◽  
Tae Hyung Lee ◽  
Jun Min Suh ◽  
Seok-Hyun Yoon ◽  
Ho Won Jang
Keyword(s):  
Dielectric Materials ◽  
Next Generation ◽  
Multilayer Ceramic Capacitors ◽  
High Capacitance ◽  
Recent Advances ◽  
Ceramic Capacitors ◽  
Critical Issues ◽  
Multilayer Ceramic

This review highlights the critical issues and recent advances in developing highly volumetric-efficient and high capacitance MLCCs from the viewpoint of designing dielectric materials.

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