scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

Energy-efficient data retention in D flip-flops using STT-MTJ

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 229-241 ◽  
Author(s):  
Kanika Monga ◽  
Nitin Chaturvedi ◽  
S. Gurunarayanan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Leakage Power ◽  
Total Power ◽  
System State ◽  
Flip Flop ◽  
Ultra Low Power ◽  
Content Type ◽  
Total Power Consumption ◽  
Standby Mode

Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Power and area-efficient register designs involving EHO algorithm

Circuit World ◽  
2020 ◽  
Vol 46 (2) ◽  
pp. 93-105
Author(s):  
Neethu Anna Sabu ◽  
Batri K.
Keyword(s):  
Low Power ◽  
Building Blocks ◽  
Leakage Power ◽  
Shift Register ◽  
Total Power ◽  
Performance Parameters ◽  
Content Type ◽  
Total Power Consumption ◽  
First Time ◽  
Area Efficient

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

scholarly journals DESIGN OF A NEW DOUBLE PULSE LATCH FLIP FLOP

2013 ◽  
pp. 149-152
Author(s):  
Nishant Tripathi ◽  
Amit Kumar ◽  
Sanjay Singh ◽  
Dhramjeet Yadav
Keyword(s):  
Pulse Generator ◽  
Cmos Technology ◽  
Leakage Power ◽  
Double Pulse ◽  
Total Power ◽  
Feature Size ◽  
Flip Flop ◽  
Timing Property ◽  
Total Power Consumption ◽  
Scale Down

This paper presents a new double pulse flip flop, which is composed of a pulse generator and latch part. DPLFF consumes less power and few transistor compare to other flip-flop. As feature size of the CMOS technology continues to scale down, leakage power has become an ever-increasing important part of the total power consumption of a chip. Double pulsed latch flip flop faster than other flip flop. This design features consumes less power. In this flip flop we modified the pulse generator to suit the circuit. The double pulse latch flip-flop has symmetric timing property. TSPICE simulation result at a frequency of 400MHz shows that proposed DPLFF consume less power compare to DPSCRFF.

scholarly journals A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

2019 ◽  
Vol 9 (1) ◽  
pp. 3
Author(s):  
Lekbir Cherif ◽  
Mohamed Chentouf ◽  
Jalal Benallal ◽  
Mohammed Darmi ◽  
Rachid Elgouri ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Negative Impact ◽  
Optimization Technique ◽  
Total Power ◽  
Flip Flop ◽  
Physical Implementation ◽  
Total Power Consumption ◽  
Bit Flip ◽  
Implementation Stage

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.

FPGA Based Low Power ROM Design Using Capacitance Scaling

2014 ◽  
Vol 1082 ◽  
pp. 471-474
Author(s):  
Meenakshi Bansal ◽  
Neha Bansal ◽  
Rishita Saini ◽  
Lakshay Kalra ◽  
Preet Mohan Singh ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Power Saving ◽  
Leakage Power ◽  
Total Power ◽  
Capacitance Scaling

An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

scholarly journals DESIGN OF A LOW POWER FLIP-FLOP USING CMOS DEEP SUBMICRON TECHNOLOGY

2013 ◽  
pp. 260-264
Author(s):  
B. FRANCIS ◽  
Y. APPARAO ◽  
B. CHINNARAO
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Short Pulse ◽  
Propagation Delay ◽  
Deep Submicron ◽  
Leakage Power ◽  
Flip Flop ◽  
Propagation Delays

This paper enumerates low power, high speed design of flip-flop having less number of transistors and only one transistor being clocked by short pulse train which is true single phase clocking (TSPC) flip-flop. Compared to Conventional flip-flop, it has 5 Transistors and one transistor clocked, thus has lesser size and lesser power consumption. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The analysis for various flip flops and latches for power dissipation and propagation delays at 0.13μm and 0.35μm technologies is carried out. The leakage power increases as technology is scaled down. The leakage power is reduced by using best technique among all run time techniques viz. MTCMOS. Thereby comparison of different conventional flip-flops, latches and TSPC flip-flop in terms of power consumption, propagation delays and product of power dissipation and propagation delay with SPICE simulation results is presented.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Sign in / Sign up

Export Citation Format

Share Document