scholarly journals An Efficient Correlation Power Analysis Attack Using Variational Mode Decomposition 

2020 ◽  
Vol 31 (1) ◽  
pp. 17-25
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Variational Mode Decomposition ◽  
Secret Key ◽  
Intrinsic Mode Functions ◽  
Side Channel Attacks ◽  
Mode Decomposition ◽  
Noisy Conditions ◽  
Correlation Power Analysis ◽  
Evaluation Board

Side channel attacks (SCAs) are now a real threat to cryptographic devices and correlation power analysis (CPA) is the most powerful attack. So far, a CPA attack usually exploits the leakage information from raw power consumption traces that collected from the attack device. In real attack scenarios, these traces collected from measurement equipment are usually contaminated by noise resulting in a decrease in attack efficiency. In this paper, we propose a variant CPA attack that exploits the leakage information from intrinsic mode functions (IMFs) of the power traces. These IMFs are the results of the variational mode decomposition (VMD) process on the raw power traces. This attack technique decreases the number of power traces for correctly recovering the secret key by approximately 13% in normal conditions and 60% in noisy conditions compared to a traditional CPA attack. Experiments were performed on power traces of AES-128 implemented in both microcontroller and FPGA by Sakura-G/W side channel evaluation board to verify the effectiveness of our method.

A Power Analysis System for Cryptographic Devices

2013 ◽  
Vol 718-720 ◽  
pp. 2376-2382
Author(s):  
Yan Ting Ren ◽  
Li Ji Wu
Keyword(s):  
Normal Mode ◽  
Power Analysis ◽  
Security Analysis ◽  
General Purpose ◽  
Side Channel ◽  
Security Level ◽  
Side Channel Attacks ◽  
Working Models ◽  
Correlation Power Analysis ◽  
Analysis System

In order to test the security of cryptographic devices against Side Channel Attacks (SCA), an automatic general-purpose power analysis system (TH-PAS-01) is designed and implemented. TH-PAS-01 is scalable and can be applied to many cryptographic devices when specific modules are installed. Using the system TH-PAS-01, correlation power analysis (CPA) are carried out on an AES chip under two working models: normal and shuffling mode. The security level of the countermeasure provided by the target chip is verified by TH-PAS-01. The experimental results show that the correct key of the AES chip is obtained with around 50,000 power traces when the chip was working under normal mode, while the whole key bits are not obtained with 960,000 power traces when the chip works under shuffling mode. The automatic general-purpose system TH-PAS-01 is feasible for security analysis on power analysis for cryptographic devices.

Leakage squeezing: Optimal implementation and security evaluation

2014 ◽  
Vol 8 (3) ◽  
Author(s):  
Claude Carlet ◽  
Jean-Luc Danger ◽  
Sylvain Guilley ◽  
Houssem Maghrebi
Keyword(s):  
Power Analysis ◽  
Hamming Distance ◽  
Security Evaluation ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Correlation Power Analysis ◽  
Zero Offset ◽  
Sophisticated Analysis ◽  
Sensitive Variable ◽  
Optimal Implementation

AbstractHardware devices can be protected against side-channel attacks by introducing one random mask per sensitive variable. The computation throughout is unaltered if the shares (masked variable and mask) are processed concomitantly, in two distinct registers. Nonetheless, this setup can still be attacked if the side-channel is squared, because this operation causes an interference between the two shares. This more sophisticated analysis is referred to as a zero-offset second-order correlation power analysis (CPA) attack. When the device leaks in Hamming distance, the countermeasure can be improved by the “leakage squeezing”. It consists in manipulating the mask through a bijection, aimed at reducing the dependency between the shares' leakage. Thus

scholarly journals Research on Fault Diagnosis of Gearbox with Improved Variational Mode Decomposition

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3510 ◽  
Author(s):  
Zhijian Wang ◽  
Junyuan Wang ◽  
Wenhua Du
Keyword(s):  
Fault Diagnosis ◽  
Signal To Noise Ratio ◽  
Optimal Number ◽  
Original Signal ◽  
Variational Mode Decomposition ◽  
Intrinsic Mode Functions ◽  
Multiple Fault ◽  
Mode Decomposition ◽  
Fault Features ◽  
Reconstructed Signal

Variational Mode Decomposition (VMD) can decompose signals into multiple intrinsic mode functions (IMFs). In recent years, VMD has been widely used in fault diagnosis. However, it requires a preset number of decomposition layers K and is sensitive to background noise. Therefore, in order to determine K adaptively, Permutation Entroy Optimization (PEO) is proposed in this paper. This algorithm can adaptively determine the optimal number of decomposition layers K according to the characteristics of the signal to be decomposed. At the same time, in order to solve the sensitivity of VMD to noise, this paper proposes a Modified VMD (MVMD) based on the idea of Noise Aided Data Analysis (NADA). The algorithm first adds the positive and negative white noise to the original signal, and then uses the VMD to decompose it. After repeated cycles, the noise in the original signal will be offset to each other. Then each layer of IMF is integrated with each layer, and the signal is reconstructed according to the results of the integrated mean. MVMD is used for the final decomposition of the reconstructed signal. The algorithm is used to deal with the simulation signals and measured signals of gearbox with multiple fault characteristics. Compared with the decomposition results of EEMD and VMD, it shows that the algorithm can not only improve the signal to noise ratio (SNR) of the signal effectively, but can also extract the multiple fault features of the gear box in the strong noise environment. The effectiveness of this method is verified.

scholarly journals Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

Cryptography ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 13
Author(s):  
Ivan Bow ◽  
Nahome Bete ◽  
Fareena Saqib ◽  
Wenjie Che ◽  
Chintan Patel ◽  
...  
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Dynamic Partial Reconfiguration ◽  
Channel Power ◽  
Diversity Techniques ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Encryption Algorithms

This paper investigates countermeasures to side-channel attacks. A dynamic partial reconfiguration (DPR) method is proposed for field programmable gate arrays (FPGAs)s to make techniques such as differential power analysis (DPA) and correlation power analysis (CPA) difficult and ineffective. We call the technique side-channel power resistance for encryption algorithms using DPR, or SPREAD. SPREAD is designed to reduce cryptographic key related signal correlations in power supply transients by changing components of the hardware implementation on-the-fly using DPR. Replicated primitives within the advanced encryption standard (AES) algorithm, in particular, the substitution-box (SBOX)s, are synthesized to multiple and distinct gate-level implementations. The different implementations change the delay characteristics of the SBOXs, reducing correlations in the power traces, which, in turn, increases the difficulty of side-channel attacks. The effectiveness of the proposed countermeasures depends greatly on this principle; therefore, the focus of this paper is on the evaluation of implementation diversity techniques.

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