Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse

In this article, we propose a hardware accelerator design using ferroelectric transistor (FeFET)-based hybrid precision synapse (HPS) for deep neural network (DNN) on-chip training. The drain erase scheme for FeFET programming is incorporated for both FeFET HPS design and FeFET buffer design. By using drain erase, high-density FeFET buffers can be integrated onchip to store the intermediate input-output activations and gradients, which reduces the energy consuming off-chip DRAM access. Architectural evaluation results show that the energy efficiency could be improved by 1.2× ∼ 2.1×, 3.9× ∼ 6.0× compared to the other HPS-based designs and emerging non-volatile memory baselines, respectively. The chip area is reduced by 19% ∼ 36% compared with designs using SRAM on-chip buffer even though the capacity of FeFET buffer is increased. Besides, by utilizing drain erase scheme for FeFET programming, the chip area is reduced by 11% ∼ 28.5% compared with the designs using body erase scheme.

A Microfabricated Bandpass Filter with Coarse-Tuning and Fine-Tuning Ability Based on IPD Process and PCB Artwork

In this paper, a bandpass filter (BPF) was developed utilizing GaAs-based integrated passive device technology which comprises an asymmetrical spiral inductor and an interleaved array capacitor, possessing two tuning modes: coarse-tuning and fine-tuning. By altering the number of layers and radius of the GaAs substrate metal spheres, capacitance variation from 0.071 to 0.106 pF for coarse-tuning, and of 0.0015 pF for fine-tuning, can be achieved. Five air bridges were employed in the asymmetrical spiral inductor to save space, contributing to a compact chip area of 0.015λ0 × 0.018λ0. The BPF chip was installed on the printed circuit board artwork with Au bonding wire and attached to a die sink. Measured results demonstrate an insertion loss of 0.38 dB and a return loss of 21.5 dB at the center frequency of 2.147 GHz. Furthermore, under coarse-tuning mode, variation in the center frequency from 1.956 to 2.147 GHz and transmission zero frequency from 4.721 to 5.225 GHz can be achieved. Under fine-tuning mode, the minimum tuning value and the average tuning value of the proposed BPF can be accurate to 1.0 MHz and 4.7 MHz for the center frequency and 1.0 MHz and 12.8 MHz for the transmission zero frequency, respectively.

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

Common Fallacies about Multivalued Circuits

For more than 60 years, many ternary or quaternary circuits have been proposed based on similar assumptions. We successively examine four of these assumptions and demonstrate that they are wrong. The fundamental reason for which m-valued combinational circuits are more complicated than the corresponding binary ones is explained. M-valued flash memories are used in USB devices because access times in not critical and a trade-off is possible between access time and chip area. If m-valued circuits are reduced to a very small niche in the binary world with semi-conductor technologies, there is a significant exception: quantum devices and computers are a true breakthrough as qbits are intrinsically multivalued. Successful m-valued circuits need m-valued devices as qbits.

A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior

In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. It features an ingenious T-shaped channel and three independent-biasing gates deposited and patterned on its left, right, and upper sides, which greatly enhance the electrostatic control ability between any two gates of all the three gates on the device channel and thus increase its turn-on current. The total current density and energy band distribution in different biasing conditions are analyzed in detail by TCAD simulations. The turn-on current, leakage current, and ratio of turn-on/off current are optimized by choosing appropriate work function and body thickness. TCAD simulation results verify the expected characteristics of the proposed Ti-TFETs in different working states. Ti-TFETs can flexibly be used to implement a logic circuit with a compact style and thus reduce the number of transistors and stack height of the circuits. It provides a new technique to reduce the chip area and power consumption by saving the number of transistors.

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

A Bootstrap Structure Directly Charged by BUS Voltage with Threshold-Based Digital Control for High-Speed Buck Converter

This article proposes a high-frequency, area-efficient high-side bootstrap circuit with threshold-based digital control (TBDC) that is directly charged by BUS voltage (DCBV). In the circuit, the voltage of the bootstrap is directly obtained from the BUS voltage instead of the on-chip low dropout regulator (LDO), which is more suitable for a high operating frequency. An area-efficient threshold-based digital control structure is used to detect the bootstrap voltage, thereby effectively preventing bootstrap under-voltage or over-voltage that may result in insufficient driving capability, increased loss, or breakdown of the power device. The design and implementation of the circuit are based on CSMC 0.25 µm 60 V BCD technology, with an overall chip area of 1.4 × 1.3 mm2, of which the bootstrap area is 0.149 mm2 and the figure-of-merit (FOM) is 0.074. The experimental results suggest that the bootstrap circuit can normally operate at 5 MHz with a maximum buck converter efficiency of 83.6%. This work plays a vital role in promoting the development of a wide range of new products and new technologies, such as integrated power supplies, new energy vehicles, and data storage centers.

Research and Design of X-band Low Noise Amplifier Based on CMOS Process

Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).

Investigation of lateral spreading current in the 4H-SiC Schottky barrier diode chip

Lateral current spreading in the 4H-SiC Schottky barrier diode (SBD) chip is investigated. The 4H-SiC SBD chips with the same vertical parameters are simulated and fabricated. The results indicate that there is a fixed spreading resistance at on-state in current spreading region for a specific chip. The linear specific spreading resistance at the on-state is calculated to be 8.6 Ω/cm in the fabricated chips. The proportion of the lateral spreading current in total forward current (P sp) is related to anode voltage and the chip area. P sp is increased with the increase in the anode voltage during initial on-state and then tends to a stable value. The stable values of P sp of the two fabricated chips are 32% and 54%. Combined with theoretical analysis, the proportion of the terminal region and scribing trench in a whole chip (K sp) is also calculated and compared with P sp. The K sp values of the two fabricated chips are calculated to be 31.94% and 57.75%. The values of K sp and P sp are close with each other in a specific chip. The calculated K sp can be used to predict that when the chip area of SiC SBD becomes larger than 0.5 cm2, the value of P sp would be lower than 10%.

A Low-Noise, High-Gain, and Small-Size UWB Mixer Utilizing Negative Impedance Technique and Source Input Method

This paper presents an ultra-wideband (UWB) down-conversion mixer with low-noise, high-gain and small-size. The negative impedance technique and source input method are applied for the proposed mixer. The negative impedance achieves the dynamic current injection and increases the mixer output impedance, which reduces the mixer flicker noise and increases its conversion gain. The source input method allows the input matching networks to be cancelled, avoiding the noise and loss introduced by the matching resistors, saving the chip area occupied by the matching inductors. The proposed mixer is designed in 45-nm SOI process provided by GlobalFoundries. The simulation results show a conversion gain of 11.4–14.3 dB, ranging from 3.1 to 10.6 GHz, a minimum noise figure of 9.8 dB, a RF port return loss of less than −11 dB, a port-to-port isolation of better than −48 dB, and a core chip area of 0.16 × 0.16 mm2. The power consumption from a 1 V supply voltage is 2.85 mW.