scholarly journals Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications

2021 ◽  
pp. 27-36
Author(s):  
Luca Bertulessi
Keyword(s):  
Cmos Technology ◽  
Frequency Synthesizers ◽  
Digital Calibration ◽  
Phase Detector ◽  
Design Parameters ◽  
Frequency Synthesis ◽  
The One ◽  
Calibration Techniques ◽  
Filter Area ◽  
Digital Loop Filter

AbstractThe fractional-N frequency synthesis based on Digital Phase Locked Loop (DPLLs) has become a conventional design approach for the new radio wireless applications. The advantage of the digitally-intensive design style is the possibility to implement low-power and very accurate digital calibration techniques. Most of these algorithms run in the background tracking PVT variations and either relax or, in some cases, completely remove the performance limitations due to analog impairments. Moreover, the digital loop filter area is practically negligible with respect to the one in analog PLLs. These benefits become even more relevant in the scaled CMOS technology nodes. This chapter identifies the design parameters of a standard DPLL architecture and proposes a novel locking scheme to overcome the intrinsic limitations of the digital frequency synthesizers approach. To prove this new scheme a sub-6 GHz fractional-N synthesizer has been implemented in 65 nm CMOS. The synthesizer has an output frequency from 3.59 GHz to 4.05 GHz. The integrated output jitter is 182fs and the power consumption of 5.28 mW from 1.2 V power supply leads to a FoM of −247.5 dB. This topology exploits a novel locking technique that guarantee a locking time of 5.6 s, for a frequency step of 364 MHz, despite the use of a single bit phase detector.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Digital Systems ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog Signals ◽  
Analog To Digital Conversion ◽  
Null Convention Logic ◽  
The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

Nonlinear Transient Response and its Sensitivity Using Finite Elements in Time

1995 ◽  
Author(s):  
Rakesh K. Kapania ◽  
Sungho Park
Keyword(s):  
Finite Elements ◽  
Transient Response ◽  
Legendre Polynomials ◽  
Design Parameters ◽  
Algebraic Equations ◽  
System Parameters ◽  
Nonlinear Transient ◽  
Linear And Nonlinear ◽  
Bilinear Formulation ◽  
The One

Abstract The bilinear formulation proposed earlier by Peters and Izadpanah to develop finite elements in time to solve undamped linear systems, is extended (and found to be readily amenable) to develop time finite elements to obtain transient responses of both linear and nonlinear, and damped and undamped systems. The formulation is used in the h-, p- and hp-versions. The resulting linear and nonlinear algebraic equations are differentiated to obtain the sensitivity of the transient response with respect to various design parameters. The present developments were tested on a series of linear and nonlinear examples and were found to yield, when compared with results obtained using other methods, excellent results for both the transient response and its sensitivity to system parameters. Mostly, the results were obtained using the Legendre polynomials as basis functions, though, in some cases other orthogonal polynomials namely, the Hermite, the Chebyshev, and integrated Legendre polynomials were also employed (but to no great advantage). A key advantage of the time finite element method, and the one often overlooked in its past applications, is the ease in which the sensitivity of the transient response with respect to various system parameters can be obtained.

Design and Fabrication of a Temperature Sensor Based on Thermopile in CMOS Technology

2003 ◽  
Author(s):  
Ioana Voiculescu ◽  
Mona Zaghloul ◽  
R. Andrew McGill
Keyword(s):  
Temperature Sensor ◽  
Silicon Oxide ◽  
Mechanical Stability ◽  
Cmos Technology ◽  
Nitride Layer ◽  
Design Parameters ◽  
Cmos Process ◽  
Post Processing ◽  
Test Chip ◽  
Optimal Geometry

This paper describes a new geometry for integrated micromachined thermopile structures. Different arrangements for the thermocouples in proximity to the heating element are examined, to optimize the accuracy of the temperature measurement. Several design parameters including thermopile lengths, and the number of thermocouples, are examined. The test chip was designed and fabricated in CMOS technology, including the appropriate opening for post-processing micromachining. The thermopile used was fabricated with polysilicon/aluminum contacts on a silicon oxide/nitride layer provided by the CMOS process. Different microbeam and bridge membrane support structures were designed for the thermopile, in order to investigate the optimal geometry for mechanical stability and to avoid structure buckling.

Influence of solid retention time on the rheology of MBR sludge

2007 ◽  
Vol 56 (8) ◽  
pp. 151-159 ◽  
Author(s):  
C. Giordano ◽  
A. Pollice ◽  
G. Laera ◽  
D. Saturno ◽  
G. Mininni
Keyword(s):  
Retention Time ◽  
Apparent Viscosity ◽  
Biomass Concentration ◽  
Rheological Behaviour ◽  
Solid Material ◽  
Design Parameters ◽  
Rheological Characterization ◽  
Solid Retention Time ◽  
The One ◽  
Definition Of

The rheological characterization is of crucial importance in sludge management both for biomass dewatering and stabilization purposes and for the definition of design parameters for sludge handling operations. The sludge retention time (SRT) has a significant influence on biomass properties in biological wastewater treatment systems and in particular in membrane bioreactors (MBR). The aim of this work is to compare the rheological behaviour of the biomass in a membrane bioreactor operated under different SRT. A bench scale MBR was operated for four years under the same conditions except for the SRT, that ranged from 20 days to complete sludge retention. The rheological properties were measured over time and the apparent viscosity was correlated with the concentration of solid material under equilibrium conditions. The three models most commonly adopted for rheological simulations were evaluated and compared in terms of their parameters. Steady state average values of these parameters were related to the equilibrium biomass concentration (MLSS). The models were tested to select the one better fitting the experimental data in terms of Mean Root Square Error (MRSE). The relationship between the apparent viscosity and the shear rate, as a function of solid concentration, was determined and proposed.

Stochastic Response Comparison between Base Isolated and Fixed-Base Structures

1997 ◽  
Vol 13 (1) ◽  
pp. 77-96 ◽  
Author(s):  
Bruno Palazzo ◽  
Luigi Petti
Keyword(s):  
Structural Response ◽  
Power Density Spectrum ◽  
Design Parameters ◽  
Elastomeric Bearings ◽  
Density Spectrum ◽  
Wide Range ◽  
Fixed Base ◽  
The One ◽  
Isolated Systems ◽  
Equivalent Linear Model

Random response of linear Base Isolated Systems, mounted on elastomeric bearings, subject to horizontal random excitations, is analyzed in comparison with the one of the fixed-base structures. Considering the superstructure motion described by its first modal contribution, a two-degree-of-freedom equivalent linear model, under stationary Gaussian excitations modelled by the modified Kanai-Tajimi power density spectrum, has been used in the analysis. The response sensitivity to design parameters for the superstructure and the isolators have been evaluated for a wide range of parameters. Optimum viscous damping and isolation degree values which minimize structural response are also obtained. Some implications of these results for the design and code requirements are discussed.

Improvement on Yield of Anisotropic Conductive Film Attach Process in TFT-LCD Module Using Taguchi Method

2010 ◽  
Vol 443 ◽  
pp. 717-722
Author(s):  
Jian Long Kuo ◽  
Kai Lun Chao ◽  
Chung Hao Hsieh
Keyword(s):  
Taguchi Method ◽  
Mechanical Design ◽  
Quality Characteristic ◽  
Design Parameters ◽  
Manufacturing Cost ◽  
Anisotropic Conductive Film ◽  
Important Concern ◽  
Conductive Film ◽  
Product Competition ◽  
The One

Anisotropic Conductive Film (ACF) is one of the important materials in LCM (Liquid Crystal Module) process, it is used in bonding process to make the driving circuit conductive. Because the price of TFT-LCD is much lower than before in recent years, the ACF cost has higher ratio in manufacture cost. The conventional long bar ACF attach unit is changed to short bar ACF attach unit in new bonding equipment. However, the new type machine was not optimized in process and mechanical design. Therefore, the failure rate of ACF attach process is much higher than the one of conventional method. This wastes the material and rework cost is also invisible. How to make the manufacturing cost down effectively and promote the product quality will be the important concern to keep the product competition. Therefore, the Taguchi method is used to analyze the problem. The ACF attach yield rate is selected to be objective function for optimization. By the optimization of quality characteristic using Taguchi method, the plasma clean speed, ACF peeling speed and ACF cutter spring setting are studied to optimize the design parameters.

Sign in / Sign up

Export Citation Format

Share Document