Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40 to 100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of -132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6µ complementary metal oxide-semiconductor process.

Measurement of EM field immunity of VCO-based ADCs in 28nm CMOS technology

Internet-of-things (IoT) devices are compact and low power. A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) benefits from scaled CMOS transistors in representing analog signals in the time domain and therefore meets those demands. However, we find the potential drawback of VCO-based ADCs for the electromagnetic susceptibility (EMS) to radio-frequency (RF) disturbances that are essentially present in IoT environment. It is exhibited that the single and even differential designs of VCO-based ADC suffer from the EMS by RF disturbance, which behaves differently from the known common-mode noise rejection. A 28-nm CMOS 10-bit VCO-ADC prototype exhibit the sensitivity against RF signals in the widely used 2.4 GHz frequency band.

A Linear VCO Using Single CFA and Analog Multipliers: Quadrature Oscillator Implementation

A new linear voltage-controlled oscillator (LVCO) implementation using single AD-844 CFA with a pair of AD-835 multiplier devices and a pair of grounded capacitors is proposed. The open-loop transfer function of the topology is analyzed wherein the concept of Short-Circuit Natural Frequency (SCNF) is applied to derive the sinusoid oscillator implementation. The proposed oscillator circuit is then restructured to yield a linear voltage-controlled quadrature oscillator (LVCQO) after appropriate cascade with a CFA-based active integrator. The oscillation frequency is linearly tunable ([Formula: see text][Formula: see text]MHz) by the multiplier control voltage ([Formula: see text]. Subsequently, a high-[Formula: see text] selective band-pass (BP) filter is derived. Effects of the CFA port roll-off parameters and its parasitic capacitors ([Formula: see text] had been analyzed to be negligible. Measured oscillator response exhibited a THD [Formula: see text]%, a linearity error ([Formula: see text]% and a phase noise figure of ([Formula: see text]104 dBc/Hz at 24-kHz offset.

Estimation of Phase Noise Transfer Function

Quantifying frequency converters’ residual phase noise is essential in various applications, including radar systems, high-speed digital communication, or particle accelerators. Multi-input signal source analyzers can perform such measurements out of the box, but the high cost limits their accessibility. Based on an analysis of phase noise transmission theory and the capabilities of popular instrumentation, we propose a technique extending the functionality of single-input devices. The method supplements absolute noise measurements with estimates of the phase noise transfer function (also called the jitter transfer function), allowing the calculation of residual noise. The details of the hardware setup used for the method verification are presented. The injection of single-tone and pseudo-random modulations to the test signal is examined. Optional employment of a spectrum analyzer can reduce the time and number of data needed for characterization. A wideband synthesizer with an integrated voltage-controlled oscillator was investigated using the method. The estimated transfer function matches a white-box model based on synthesizer’s structure and values of loop components. The first results confirm the validity of the proposed technique.