Design of Low Power Low Jitter Delay Locked Loop in 45 nm CMOS

2021 ◽  
pp. 147-162
Author(s):  
P. Latha ◽  
R. Sivakumar ◽  
Y. V. Ramana Rao ◽  
Thamer Al-Rousan
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Jitter Delay ◽  
Low Jitter

A wide range delay locked loop for low power and low jitter applications

2017 ◽  
Vol 46 (3) ◽  
pp. 401-414 ◽  
Author(s):  
Motahhareh Estebsari ◽  
Mohammad Gholami ◽  
Mohammad Javad Ghahramanpour
Keyword(s):  
Low Power ◽  
Delay Locked Loop ◽  
Wide Range ◽  
Low Jitter

A fast locking and low jitter delay-locked loop using DHDL

2003 ◽  
Vol 38 (2) ◽  
pp. 343-346 ◽  
Author(s):  
Hsiang-Hui Chang ◽  
Jyh-Woei Lin ◽  
Shen-Iuan Liu
Keyword(s):  
Delay Locked Loop ◽  
Jitter Delay ◽  
Low Jitter

Analysis and design of a low jitter delay‐locked loop using lock state detector

2021 ◽  
Vol 49 (5) ◽  
pp. 1410-1419 ◽  
Author(s):  
Shahram Modanlou ◽  
Gholamreza Ardeshir ◽  
Mohammad Gholami
Keyword(s):  
Analysis And Design ◽  
Delay Locked Loop ◽  
Jitter Delay ◽  
Low Jitter ◽  
State Detector

scholarly journals A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

Electronics ◽  
2021 ◽  
Vol 10 (2) ◽  
pp. 177
Author(s):  
Dongjun Park ◽  
Sungwook Choi ◽  
Jongsun Kim
Keyword(s):  
Sampling Technique ◽  
Cmos Process ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Delta Sigma Modulator ◽  
Correlated Double Sampling ◽  
Delta Sigma ◽  
Fast Power ◽  
Low Jitter ◽  
Reference Clock

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

2021 ◽  
pp. 1-1
Author(s):  
Younghyun Lim ◽  
Juyeop Kim ◽  
Yongwoo Jo ◽  
Jooeun Bang ◽  
Jaehyouk Choi
Keyword(s):  
Low Power ◽  
Power Frequency ◽  
Low Jitter ◽  
Lock In
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