An Asynchronous Viterbi Decoder for Low-Power Applications

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-39762-5_53 ◽

2003 ◽

pp. 471-480 ◽

Author(s):

B. Javadi ◽

M. Naderi ◽

H. Pedram ◽

A. Afzali-Kusha ◽

M. K. Akbari

Keyword(s):

Low Power ◽

Viterbi Decoder

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Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems

1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258) ◽

10.1109/icassp.1999.758298 ◽

1999 ◽

Author(s):

H. Suzuki ◽

Yun-Nan Chang ◽

K.K. Parhi

Keyword(s):

Low Power ◽

Wide Band ◽

Viterbi Decoder ◽

Next Generation ◽

Cdma Systems ◽

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A high-speed low-power pipelined Viterbi Decoder: breaking the ACS-bottleneck

The 2010 International Conference on Green Circuits and Systems ◽

10.1109/icgcs.2010.5543044 ◽

2010 ◽

Author(s):

Kelvin Yi-Tse Lai

Keyword(s):

Low Power ◽

Viterbi Decoder

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Low-power multi-standard Viterbi decoder for wireless communication applications

International Journal of Electronics Letters ◽

10.1080/21681724.2015.1028472 ◽

2015 ◽

Vol 4 (2) ◽

pp. 228-238 ◽

Author(s):

Chu Yu ◽

Bor-Shing Lin ◽

Po-Hsun Cheng ◽

Yu-Shan Su

Keyword(s):

Wireless Communication ◽

Low Power ◽

Viterbi Decoder

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Design of a low-power Viterbi decoder for wireless communications

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003 ◽

10.1109/icecs.2003.1302037 ◽

2004 ◽

Author(s):

F. Ghanipour ◽

A.R. Nabavi

Keyword(s):

Wireless Communications ◽

Low Power ◽

Viterbi Decoder

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Transformation of ACS module to CSA module of low-power Viterbi decoder for digital wireless communication applications

2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI) ◽

10.1109/icacci.2013.6637182 ◽

2013 ◽

Author(s):

Sayak Bhowal

Keyword(s):

Wireless Communication ◽

Low Power ◽

Viterbi Decoder

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A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2010.1402 ◽

2010 ◽

Vol 1 (4) ◽

pp. 14-22 ◽

Author(s):

S.L Haridas ◽

N.K Choudhari

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Wireless Applications ◽

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A low power asynchronous Viterbi decoder using minimum transition hybrid register exchange method

2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon) ◽

10.1109/smarttechcon.2017.8358357 ◽

2017 ◽

Author(s):

Surekha K. Tadse ◽

S. L. Haridas

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Exchange Method

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838266 ◽

2005 ◽

Vol 52 (2) ◽

pp. 350-365 ◽

Author(s):

Man Guo ◽

M.O. Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation

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Design of Low-Power Memory-Efficient Viterbi Decoder

2007 IEEE Workshop on Signal Processing Systems ◽

10.1109/sips.2007.4387532 ◽

2007 ◽

Author(s):

Lupin Chen ◽

Jinjin He ◽

Zhongfeng Wang

Keyword(s):

Low Power ◽

Viterbi Decoder ◽

Memory Efficient

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VLSI implementation of a high-speed and low-power punctured Viterbi decoder

2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering. TENCOM '02. Proceedings. ◽

10.1109/tencon.2002.1180342 ◽

2003 ◽

Author(s):

Li Qiao ◽

You Yuxin ◽

Wang Jinxiang ◽

Ye Yizheng

Keyword(s):

Low Power ◽

Vlsi Implementation ◽

Viterbi Decoder

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