Approaches for FPGA Design Assurance

Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design. In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design. We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.

The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations

N-body methods are one of the essential algorithmic building blocks of high-performance and parallel computing. Previous research has shown promising performance for implementing n-body simulations with pairwise force calculations on FPGAs. However, to avoid challenges with accumulation and memory access patterns, the presented designs calculate each pair of forces twice, along with both force sums of the involved particles. Also, they require large problem instances with hundreds of thousands of particles to reach their respective peak performance, limiting the applicability for strong scaling scenarios. This work addresses both issues by presenting a novel FPGA design that uses each calculated force twice and overlaps data transfers and computations in a way that allows to reach peak performance even for small problem instances, outperforming previous single precision results even in double precision, and scaling linearly over multiple interconnected FPGAs. For a comparison across architectures, we provide an equally optimized CPU reference, which for large problems actually achieves higher peak performance per device, however, given the strong scaling advantages of the FPGA design, in parallel setups with few thousand particles per device, the FPGA platform achieves highest performance and power efficiency.

Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure

Cloud deployments now increasingly exploit Field-Programmable Gate Array (FPGA) accelerators as part of virtual instances. While cloud FPGAs are still essentially single-tenant, the growing demand for efficient hardware acceleration paves the way to FPGA multi-tenancy. It then becomes necessary to explore architectures, design flows, and resource management features that aim at exposing multi-tenant FPGAs to the cloud users. In this article, we discuss a hardware/software architecture that supports provisioning space-shared FPGAs in Kernel-based Virtual Machine (KVM) clouds. The proposed hardware/software architecture introduces an FPGA organization that improves hardware consolidation and support hardware elasticity with minimal data movement overhead. It also relies on VirtIO to decrease communication latency between hardware and software domains. Prototyping the proposed architecture with a Virtex UltraScale+ FPGA demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization, which is one of the goals of virtualization. Overall, our FPGA design achieved about 2× higher maximum frequency than the state of the art and a bandwidth reaching up to 28 Gbps on 32-bit data width.

xDNN: Inference for Deep Convolutional Neural Networks

We present xDNN, an end-to-end system for deep-learning inference based on a family of specialized hardware processors synthesized on Field-Programmable Gate Array (FPGAs) and Convolution Neural Networks (CNN). We present a design optimized for low latency, high throughput, and high compute efficiency with no batching. The design is scalable and a parametric function of the number of multiply-accumulate units, on-chip memory hierarchy, and numerical precision. The design can produce a scale-down processor for embedded devices, replicated to produce more cores for larger devices, or resized to optimize efficiency. On Xilinx Virtex Ultrascale+ VU13P FPGA, we achieve 800 MHz that is close to the Digital Signal Processing maximum frequency and above 80% efficiency of on-chip compute resources. On top of our processor family, we present a runtime system enabling the execution of different networks for different input sizes (i.e., from 224× 224 to 2048× 1024). We present a compiler that reads CNNs from native frameworks (i.e., MXNet, Caffe, Keras, and Tensorflow), optimizes them, generates codes, and provides performance estimates. The compiler combines quantization information from the native environment and optimizations to feed the runtime with code as efficient as any hardware expert could write. We present tools partitioning a CNN into subgraphs for the division of work to CPU cores and FPGAs. Notice that the software will not change when or if the FPGA design becomes an ASIC, making our work vertical and not just a proof-of-concept FPGA project. We show experimental results for accuracy, latency, and power for several networks: In summary, we can achieve up to 4 times higher throughput, 3 times better power efficiency than the GPUs, and up to 20 times higher throughput than the latest CPUs. To our knowledge, we provide solutions faster than any previous FPGA-based solutions and comparable to any other top-of-the-shelves solutions.

Development of an Open PXIe System based on FPGA Modules

<p>PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe platform comprises of modules that are housed in a 3U Eurocard form factor chassis. The platform utilise the PCIe bus standard to enable high-speed data transfer, suitable for a range of applications. However, the platform is inherently complex, contains proprietary IP and is prohibitively expensive for most researchers and engineers who wish to utilise a modular instrumentation system. To overcome these barriers, the beginnings of an open PXIe platform has been developed. This consists of two open PXIe modules utilising modular FPGA technology. The first module is the System Controller, which introduces an embedded Linux solution and open-source PCIe driver to the platform. To simplify software development, user applications can utilise the drivers API without using kernel-level code. On the System Controller FPGA fabric is a root-port implementation that allows communication with peripheral modules. The second modules is a general purpose Peripheral Module that provides various I/O standards that users can utilise in their FPGA design, and a dedicated PCIe generation 2 x4 link with the System Controller. In the FPGA fabric of the Peripheral Module is a PCIe-DMA engine that facilitates data transfer between the two modules. The open nature and modular design will allow more economical and more flexible solutions, which will be appealing to a wide range of potential users. In addition, an example user application is developed for this system to show case the overall functionality the modules, with transfer speeds of 100 MB/s.</p>

Development of an Open PXIe System based on FPGA Modules

<p>PXIe is a instrumentation platform that is used as the basis for developing test equipment, modular electronic instruments and automated test systems. A typical PXIe platform comprises of modules that are housed in a 3U Eurocard form factor chassis. The platform utilise the PCIe bus standard to enable high-speed data transfer, suitable for a range of applications. However, the platform is inherently complex, contains proprietary IP and is prohibitively expensive for most researchers and engineers who wish to utilise a modular instrumentation system. To overcome these barriers, the beginnings of an open PXIe platform has been developed. This consists of two open PXIe modules utilising modular FPGA technology. The first module is the System Controller, which introduces an embedded Linux solution and open-source PCIe driver to the platform. To simplify software development, user applications can utilise the drivers API without using kernel-level code. On the System Controller FPGA fabric is a root-port implementation that allows communication with peripheral modules. The second modules is a general purpose Peripheral Module that provides various I/O standards that users can utilise in their FPGA design, and a dedicated PCIe generation 2 x4 link with the System Controller. In the FPGA fabric of the Peripheral Module is a PCIe-DMA engine that facilitates data transfer between the two modules. The open nature and modular design will allow more economical and more flexible solutions, which will be appealing to a wide range of potential users. In addition, an example user application is developed for this system to show case the overall functionality the modules, with transfer speeds of 100 MB/s.</p>

Development of a PXI Express Peripheral Module and Data Transfer Platform

<p>Magritek, a company who specialise in NMR and MRI devices, required a new backplane communication solution for transmission of data. Possible options were evaluated and it was decided to move to the PXI Express instrumentation standard. As a first step of moving to this system, an FPGA based PXI Express Peripheral Module was designed and constructed. In order to produce this device, details on PXI Express boards and the signals required were researched, and schematics produced. These were then passed onto the board designer who incorporated the design with other design work at Magritek to produce a PXI Express Peripheral Module for use as an NMR transceiver board. With the board designed, the FPGA was configured to provide PXI Express functionality. This was designed to allow PCI Express transfers at high data speeds using Direct Memory Access (DMA). The PXI Express Peripheral board was then tested and found to function correctly, providing Memory Write speeds of 228 MB/s and Memory Read speeds of 162 MB/s. Also, to provide a test system for this physical and FPGA design, backplanes were designed to test communication between PXI Express modules.</p>

Development of a PXI Express Peripheral Module and Data Transfer Platform

<p>Magritek, a company who specialise in NMR and MRI devices, required a new backplane communication solution for transmission of data. Possible options were evaluated and it was decided to move to the PXI Express instrumentation standard. As a first step of moving to this system, an FPGA based PXI Express Peripheral Module was designed and constructed. In order to produce this device, details on PXI Express boards and the signals required were researched, and schematics produced. These were then passed onto the board designer who incorporated the design with other design work at Magritek to produce a PXI Express Peripheral Module for use as an NMR transceiver board. With the board designed, the FPGA was configured to provide PXI Express functionality. This was designed to allow PCI Express transfers at high data speeds using Direct Memory Access (DMA). The PXI Express Peripheral board was then tested and found to function correctly, providing Memory Write speeds of 228 MB/s and Memory Read speeds of 162 MB/s. Also, to provide a test system for this physical and FPGA design, backplanes were designed to test communication between PXI Express modules.</p>