A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder

2014 ◽  
Vol 34 (6) ◽  
pp. 2015-2035
Author(s):  
Michaelraj Kingston Roberts ◽  
Ramesh Jayabalan
Keyword(s):  
Ldpc Decoder ◽  
Area Efficient

An area efficient LDPC decoder using a reduced complexity min-sum algorithm

Integration ◽  
2012 ◽  
Vol 45 (2) ◽  
pp. 141-148 ◽  
Author(s):  
Vikram Arkalgud Chandrasetty ◽  
Syed Mahfuzul Aziz
Keyword(s):  
Ldpc Decoder ◽  
Reduced Complexity ◽  
Area Efficient

Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA

2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin
Keyword(s):  
Energy Efficient ◽  
Communication Systems ◽  
Average Power ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Hardware Complexity ◽  
Chip Area ◽  
Ldpc Decoder ◽  
Area Efficient

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution

2012 ◽  
Vol E95-C (4) ◽  
pp. 478-486
Author(s):  
Changsheng ZHOU ◽  
Yuebin HUANG ◽  
Shuangqu HUANG ◽  
Yun CHEN ◽  
Xiaoyang ZENG
Keyword(s):  
Conflict Resolution ◽  
Ldpc Decoder ◽  
Area Efficient

scholarly journals Memory Compact High-Speed QC-LDPC Decoder Based on FPGA

2019 ◽  
Vol 37 (3) ◽  
pp. 515-522
Author(s):  
Tianjiao Xie ◽  
Bo Li ◽  
Mao Yang ◽  
Zhongjiang Yan
Keyword(s):  
High Speed ◽  
Clock Cycle ◽  
Fpga Implementation ◽  
Maximum Frequency ◽  
Ldpc Decoder ◽  
Memory Strategies ◽  
Multiple Data ◽  
Decoder Architecture ◽  
Place And Route ◽  
Area Efficient

In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture

2017 ◽  
Vol 17 (6) ◽  
pp. 845-853 ◽  
Author(s):  
Sabooh Ajaz ◽  
Tram Thi Bao Nguyen ◽  
Hanho Lee
Keyword(s):  
Ldpc Decoder ◽  
Decoder Architecture ◽  
Area Efficient
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