Area efficient LDPC decoder design for parallel layered decoding

2011 9th IEEE International Conference on ASIC ◽

10.1109/asicon.2011.6157296 ◽

2011 ◽

Author(s):

Yuan Yao ◽

Fan Ye ◽

Junyan Ren

Keyword(s):

Ldpc Decoder ◽

Layered Decoding ◽

Decoder Design ◽

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Area efficient half row pipelined layered LDPC decoder for gigabit wireless communications

2015 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2015.7401700 ◽

2015 ◽

Author(s):

Sabooh Ajaz ◽

Hanho Lee

Keyword(s):

Wireless Communications ◽

Ldpc Decoder ◽

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Error Resilience and Energy Efficiency: An LDPC Decoder Design Study

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.3850/9783981537079_0023 ◽

2016 ◽

Author(s):

Philipp Schläfer ◽

Chu-Hsiang Huang ◽

Clayton Schoeny ◽

Christian Weis ◽

Yao Li ◽

...

Keyword(s):

Energy Efficiency ◽

Error Resilience ◽

Design Study ◽

Ldpc Decoder ◽

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GF(q) LDPC decoder design for FPGA implementation

2013 IEEE 10th Consumer Communications and Networking Conference (CCNC) ◽

10.1109/ccnc.2013.6488484 ◽

2013 ◽

Author(s):

W. Sulek ◽

M. Kucharczyk ◽

G. Dziwoki

Keyword(s):

Fpga Implementation ◽

Ldpc Decoder ◽

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Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes

2014 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2014.6865152 ◽

2014 ◽

Author(s):

Chih-Wen Yang ◽

Xin-Ru Lee ◽

Chih-Lung Chen ◽

Hsie-Chia Chang ◽

Chen-Yi Lee

Keyword(s):

Decoder Design ◽

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Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms

IEICE Transactions on Electronics ◽

10.1093/ietele/e90-c.10.1964 ◽

2007 ◽

Vol E90-C (10) ◽

pp. 1964-1971

Author(s):

Q. WANG ◽

K. SHIMIZU ◽

T. IKENAGA ◽

S. GOTO

Keyword(s):

Ldpc Decoder ◽

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An area efficient LDPC decoder using a reduced complexity min-sum algorithm

Integration ◽

10.1016/j.vlsi.2011.08.002 ◽

2012 ◽

Vol 45 (2) ◽

pp. 141-148 ◽

Author(s):

Vikram Arkalgud Chandrasetty ◽

Syed Mahfuzul Aziz

Keyword(s):

Ldpc Decoder ◽

Reduced Complexity ◽

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An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2010.2042255 ◽

2010 ◽

Vol 45 (4) ◽

pp. 843-855 ◽

Author(s):

Zhengya Zhang ◽

Venkat Anantharam ◽

Martin J. Wainwright ◽

Borivoje Nikolic

Keyword(s):

Ldpc Decoder ◽

Decoder Design ◽

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An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm

IEICE Electronics Express ◽

10.1587/elex.12.20150356 ◽

2015 ◽

Vol 12 (13) ◽

pp. 20150356-20150356

Author(s):

Song Guo ◽

Yong Dou ◽

Yuanwu Lei ◽

Rongchun Li ◽

Yu Li

Keyword(s):

Decoding Algorithm ◽

Ldpc Decoder ◽

Layered Decoding

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A solution for memory collision in semi-parallel FPGA-based LDPC decoder design

2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2007.4487366 ◽

2007 ◽

Author(s):

Radivoje Zarubica ◽

Stephen G. Wilson

Keyword(s):

Ldpc Decoder ◽

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A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder

Circuits Systems and Signal Processing ◽

10.1007/s00034-014-9949-4 ◽

2014 ◽

Vol 34 (6) ◽

pp. 2015-2035

Author(s):

Michaelraj Kingston Roberts ◽

Ramesh Jayabalan

Keyword(s):

Ldpc Decoder ◽

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