Monolithic imagers contain the photosensitive elements as well as the read-out IC (ROIC) on the same substrate. Backside thinning on carrier enables efficient collection of photo-generated carriers through back illumination, resulting in almost 100% fill factor. This contrary to front side illumination where light loss is introduced by reflection on metal interconnects. Together with an optimized backside ARC coating, high quantum efficiency (QE) can be achieved. Hybrid imagers consist of a detector array that is produced separately and hybridized on a ROIC. A fully-hybrid backside illuminated imager has more flexibility because the detector array and the ROIC can be separately optimized to the needs of the application leading towards further improvement on QE and inter pixel cross talk. Fully processed thinned diode arrays were flip-chipped onto the ROIC by means of an Indium bump per pixel. The choice of the bump type is very critical for yielding imager assemblies, or more in general, 3D assemblies. The Indium bump process has however limited fab compatibility to evolve towards a production mature hybrid imager process. Therefore an alternative electroplated CuSn micro bump process is described. We report an average daisy chain yield above 90% for die-to-die assemblies with CuSn bumps. Measurements were performed on a dedicated 1M bump area array test design with very long daisy chains of bumps on a 20μm pitch. Processing aspects like choice of plating seed layer, the influence of cleaning agents and seed layer etchants on the micro bump performance are being discussed. Finally, the impact on the daisy chain yield after thermal cycling is shown.
Development of an Indium bump bond process for silicon pixel detectors at PSI