scholarly journals Design of interfaces between high speed data converters and high performance FPGAs for software defined radio applications

2019 ◽  
Vol 71 (4) ◽  
pp. 601-614 ◽  
Author(s):  
Mahadevan Balakrishnan ◽  
Khalim Amjad Meerja ◽  
Kishore Kumar Gundugonti ◽  
Sri Rama Krishna Kalva
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
High Performance ◽  
Data Converters ◽  
High Speed Data

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

Lane Detection Algorithm Based on Genetic Algorithm and its Parallel Computing Realization

2012 ◽  
Vol 479-481 ◽  
pp. 65-70
Author(s):  
Xiao Hui Zhang ◽  
Liu Qing ◽  
Mu Li
Keyword(s):  
Genetic Algorithm ◽  
Data Transmission ◽  
High Speed ◽  
High Performance ◽  
Large Data ◽  
Detection Algorithm ◽  
Lane Detection ◽  
The Road ◽  
Time Problem ◽  
High Speed Data

Based on the target detection of alignment template, the paper designs a lane alignment template by using correlation matching method, and combines with genetic algorithm for template stochastic matching and optimization to realize the lane detection. In order to solve the real-time problem of lane detection algorithm based on genetic algorithm, this paper uses the high performance multi-core DSP chip TMS320C6474 as the core, combines with high-speed data transmission technology of Rapid10, realizes the hardware parallel processing of the lane detection algorithm. By Rapid10 bus, the data transmission speed between the DSP and the DSP can reach 3.125Gbps, it basically realizes transmission without delay, and thereby solves the high speed transmission of the large data quantity between processor. The experimental results show that, no matter the calculated lane line, or the running time is better than the single DSP and PC at the parallel C6474 platform. In addition, the road detection is accurate and reliable, and it has good robustness.

Design of Universal Signal Processing Machine Based on Multiple DSP

2013 ◽  
Vol 321-324 ◽  
pp. 1241-1244
Author(s):  
Yang Jian ◽  
Yu Hao Liu ◽  
Xi Jing Zhao ◽  
Hao Ming Chen
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Multiple Channel ◽  
Processing Machine ◽  
Large Memory ◽  
High Speed Data ◽  
Board Level

With the development and application of technique on high speed digital signal processing, wide bandwidth processing, high-speed data exchanging and flexible interlink structure have been the developing trend of modern high performance signal processing machine. In this paper, one universal signal processing machine is designed based on six pieces of ADSP-TS201 TigerSHARC processors, which owns good characteristics such as: large memory, excellent processing and data-exchanging performance, reconstitution, good expansibility. This signal processing machine adopts 64Bit, 66MHz CPCI bus standard and supports the function of extending processing performance by interlinking multiple boards. The high-speed data-exchanging is realized with multiple channel optical fiber. Furthermore, it owns board-level BIT function.

Design of a Small-Sized High-Speed Data Storage Module Based on FPGA

2014 ◽  
Vol 912-914 ◽  
pp. 1556-1560
Author(s):  
Sheng Kun Li ◽  
Cheng Qun Chu ◽  
Hai Liang Chen ◽  
Fang Ma
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
High Speed ◽  
High Performance ◽  
Data Access ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Unit ◽  
Field Programmable ◽  
High Speed Data

The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

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