Measurement of the lattice constant of Si-Ge heteroepitaxial layers grown on a silicon substrate

The prospect of technical applications has induced a lot of interest in the atomic structure of the GaAs on Si(100) interface and the defects in its vicinity which are often studied by high resolution transmission electron microscopy. The interface structure is determined by the 4.1% lattice constant mismatch between GaAs and Si, the large difference between the thermal expansion coefficients and the polar/nonpolar nature of the GaAs on Si interface. The lattice constant mismatch is compensated by misfit dislocations which are characterized by a/2<110> Burgers vectors b which are oriented parallel or inclined on {111} planes with respect to the interface. Stacking faults are also frequently observed. They are terminated by partial dislocations with b = a/6<112> on {111} planes. In this report, the atomic structure of stair rod misfit dislocations is analysed which are located at the intersection line of two stacking faults at the interface.A very thin, discontinous film of GaAs has been grown by MBE on a Si(100) substrate. Fig.1.a. shows an interface section of a 27 nm wide GaAs island along [110] containing a stair rod dislocation. The image has been taken with a JEOL 2000EX with a spherical aberration constant Cs = 1 mm, a spread of focus Δz = 10 nm and an angle of beam convergence ϑ of 2 mrad.

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InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.677 ◽

2014 ◽

Vol E97.C (7) ◽

pp. 677-682

Author(s):

Sung YUN WOO ◽

Young JUN YOON ◽

Jae HWA SEO ◽

Gwan MIN YOO ◽

Seongjae CHO ◽

...

Keyword(s):

Silicon Substrate ◽

Field Effect ◽

Field Effect Transistor ◽

Effect Transistor

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Effect of the structural changes on the mechanical properties of the sintered films

JOURNAL OF ADVANCES IN PHYSICS ◽

10.24297/jap.v12i1.168 ◽

2016 ◽

Vol 12 (1) ◽

pp. 4141-4144

Author(s):

Garima Jain

Keyword(s):

Crystallite Size ◽

Lattice Constant ◽

Structural Changes ◽

Structural Investigation ◽

Energy Gap ◽

Lattice Parameter ◽

Metal Chalcogenides ◽

Optical Energy Gap ◽

Tin Telluride ◽

Physical Quantities

Polycrystalline films of tin telluride were prepared by sintering technique. The structural investigation of the films with different thicknesses enables to determine lattice parameter, crystallite size and strain existing in the films. The XRD traces showed that strain was tensile in nature. The crystallite size increases with thickness while strain decreases. Higher the value of tensile strain, larger is the lattice constant. The optical energy gap shows a descending nature with increasing strain and so with the lattice constant. Such an attempt made to delve into interdependence of basic physical quantities helps to explore the properties of SnTe and utilize it as an alternative to heavy metal chalcogenides in various technological applications. Â

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Transport Properties Of Metallic Nanowires On Silicon Substrate

i-manager s Journal on Material Science ◽

10.26634/jms.2.1.2760 ◽

2014 ◽

Vol 2 (1) ◽

pp. 20-23

Author(s):

Jaskiran Kaur ◽

◽

Surinder Singh ◽

Keyword(s):

Transport Properties ◽

Silicon Substrate ◽

Metallic Nanowires

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Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0092 ◽

2010 ◽

Author(s):

J.G. van Hassel ◽

Xiao-Mei Zhang

Keyword(s):

Failure Analysis ◽

Case Studies ◽

Silicon Substrate ◽

Processing Technique ◽

Electrical Characteristics ◽

Localization Method ◽

The Right ◽

Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

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Studies on a Novel Qualification Method of Silicon Nitride Layer

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0186 ◽

2016 ◽

Author(s):

Younan Hua ◽

Bingsheng Khoo ◽

Henry Leong ◽

Yixin Chen ◽

Eason Chan ◽

...

Keyword(s):

Silicon Nitride ◽

Silicon Substrate ◽

Nitride Layer ◽

Passivation Layer ◽

Wafer Fabrication ◽

Wafer Surface ◽

Si3n4 Layer ◽

Silicon Nitride Layer ◽

Passivation Layers ◽

Pinhole Test

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

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