Analysis of Retention Time Degradation Caused by Electrostatic Potential Variation between Adjacent Bit-Line and Adjacent Contact Node in DRAM

Systematic retention failure related on the adjacent electrostatic potential is studied with sub 20nm DRAM. Unlike traditional retention failures which are caused by gate induced drain leakage or junction leakage, this failure is influenced by the combination of adjacent signal line and adjacent contact node voltage. As the critical dimension between adjacent active and the adjacent signal line and contact node is scaled down, the effect of electric field caused by adjacent node on storage node is increased gradually. In this paper, we will show that the relationship between the combination electric field of adjacent nodes and the data retention characteristics and we will demonstrate the mechanism based on the electrical analysis and 3D TCAD simulation simultaneously.

Body Effect Measurement in DRAM Cell Transistor Using Memory Test System

Body effect is the key characteristic of DRAM cell transistor. Conventional method uses a TEG structure for body effect measurement. But this measurement is not accurate, because TEG structure has only several transistors and it is located outside of the DRAM die. This paper suggests a viable method for measuring DRAM cell transistor body effect. It uses a memory test system for fast, massive, nondestructive measurement. Newly developed method can measure 100,000 DRAM cell body effects in two minute, without sample damage. The test gives one median value and 100,000 individual values of body effects. Median value of measured body effects is equal to the TEG body effect. An individual DRAM cell body effect has a correlation with the fin height.

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

Visible Laser Probing (VLP) with GaP Solid Immersion Lens Demonstrating 110 nm Resolution in Common Laser Probing Applications

This paper demonstrates a breakthrough method of visible laser probing (VLP), including an optimized 577 nm laser microscope, visible-sensitive detector, and an ultimate-resolution gallium phosphide-based solid immersion lens on the 10 nm node, showing a 110 nm resolution. This is 2x better than what is achieved with the standard suite of probing systems using typical infrared (IR) wavelengths today. Since VLP provides a spot diameter reduction of 0.5x over IR methods, it is reasonable, based simply on geometry, to project that VLP using the 577 nm laser will meet the industry needs for laser probing for both the 10 nm and 7 nm process nodes. Based on its high level of optimization, including high resolution and specialized solid immersion lens, it is highly likely that this VLP technology will be one of the last optically-based fault isolation methods successfully used.

Combining Current Imaging, EBIC/EBAC, and Electrical Probing for Fast and Reliable In-Situ Electrical Fault Isolation

Using a compact nanoprobing setup comprising eight probe tips attached to piezo-driven micromanipulators, various techniques for fault isolation are performed on 28 nm samples inside an SEM. The recently implemented Current Imaging technique is used to quickly image large arrays of contacts providing a means of locating faults.

Nanoscale Capacitance and Capacitance-Voltage Curves for Advanced Characterization of Electrical Properties of Si and GaN Structures Using Scanning Microwave Impedance Microscopy

The use of Atomic Force Microscopy (AFM) electrical measurement modes is a critical tool for the study of semiconductor devices and process development. A relatively new electrical mode, scanning microwave impedance microscopy (sMIM), measures a material’s change in permittivity and conductivity at the scale of an AFM probe tip [1]. sMIM provides the real and imaginary impedance (Re(Z) and Im(Z)) of the probe-sample interface. By measuring the reflected microwave signal as a sample of interest is imaged with an AFM, we can in parallel capture the variations in permittivity and conductivity and, for doped semiconductors, variations in the depletion-layer geometry. An existing technique for characterizing doped semiconductors, scanning capacitance microscopy, modulates the tip-sample bias and detects the tip-sample capacitance with a lock-in amplifier. A previous study compares sMIM to SCM and highlights the additional capabilities of sMIM [2], including examples of nano-scale capacitance-voltage curves. In this paper we focus on the detailed mechanisms and capabilities of the nano-scale C-V curves and the ability to extract semiconductor properties from them. This study includes analytical and finite element modeling of tip bias dependent depletion-layer geometry and impedance. These are compared to experimental results on reference samples for both doped Si and GaN doped staircases to validate the systematic response of the sMIM-C (capacitive) channel to the doping concentration.

Two-Dimensional Local Deep-Level Transient Spectroscopy Imaging Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

A new technique for local deep level transient spectroscopy (DLTS) imaging using super-higher-order scanning nonlinear dielectric microscopy is proposed. Using this technique. SiCVSiC structure samples with different post oxidation annealing conditions were measured. We observed that the local DLTS signal decreases with post oxidation annealing (POA), which agrees with the well-known phenomena that POA reduces trap density. Furthermore, obtained local DLTS images had dark and bright areas, which is considered to show the trap distribution at/near SiCVSiC interface.

Optimizing Gas-Assisted Processes for Ga and Xe FIB Circuit Edit Application

Despite commercial availability of a number of gas-enhanced chemical etches for faster removal of the material, there is still lack of understanding about how to take into account ion implantation and the structural damage by the primary ion beam during focused ion beam gas-assisted etching (FIB GAE). This paper describes the attempt to apply simplified beam reconstruction technique to characterize FIB GAE within single beam width and to evaluate the parameters critical for editing features with the dimensions close to the effective ion beam diameter. The approach is based on reverse-simulation methodology of ion beam current profile reconstruction. Enhancement of silicon dioxide etching with xenon difluoride precursor in xenon FIB with inductively coupled plasma ion source appears to be high and relatively uniform over the cross-section of the xenon beam, making xenon FIB potentially suitable platform for selective removal of materials in circuit edit application.

Failure Localization in a Multistage S-Band Power Amplifier

During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.