scholarly journals PVT-Compensated Low Voltage LNA Based on Variable Current Source for Low Power Applications

2021 ◽  
pp. 154042
Author(s):  
Sajad Nejadhasan ◽  
Fatemeh Zaheri ◽  
Ebrahim Abiri ◽  
Mohammad Reza Salehi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Current Source

scholarly journals A Transformerless Single-Phase Current Source Inverter Topology and Control for Photovoltaic Applications

Energies ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 2011 ◽  
Author(s):  
Jorge Cardoso ◽  
Nimrod Vazquez ◽  
Claudia Hernandez ◽  
Joaquin Vaquero
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Single Phase ◽  
Low Voltage ◽  
Neutral Line ◽  
Current Source ◽  
Total Efficiency ◽  
Pv System ◽  
Phase Current ◽  
Current Source Inverter

Low power grid-tied photovoltaic (PV) generation systems increasingly use transformerless inverters. The elimination of the transformer allows smaller, lighter and cheaper systems, and improves the total efficiency. However, a leakage current may appear, flowing from the grid to the PV panels through the existing parasitic capacitance between them, since there is no galvanic isolation. As a result, electromagnetic interferences and security issues arise. This paper presents a novel transformerless single-phase Current Source Inverter (CSI) topology with a reduced inductor, compared to conventional CSIs. This topology directly connects the neutral line of the grid to the negative terminal of the PV system, referred as common mode configuration, eliminating this way, theoretically, the possibility of any leakage current through this terminal. The switches control is based on a hysteresis current controller together with a combinational logic circuitry and it is implemented in a digital platform based on National Instruments Technology. Results that validate the proposal, based on both simulations and tests of a low voltage low power prototype, are presented.

scholarly journals A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference: Design and Application

2015 ◽  
Vol 10 (2) ◽  
pp. 74-80
Author(s):  
Alfredo Olmos ◽  
Fabricio Ferreira ◽  
Fernando Paixão Cortes ◽  
Fernando Chavez ◽  
Marcelo Soares Lubaszewski
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Current Source ◽  
Design Procedure ◽  
Voltage Reference ◽  
Threshold Voltages ◽  
Strong Inversion ◽  
Design And Application

This paper presents the design and application of a CMOS sub-1V voltage reference using a 2-transistor Self-Cascode MOSFET (SCM) structure able to get low power consumption, temperature compensation, and small area. An efficient design procedure applied to this simple topology relying on NMOS transistors with different threshold voltages allows attaining large immunity against bias current and supply voltage variations. The two transistors can operate in weak, moderate, or strong inversion making the design flexible in terms of area and power consumption. Implemented in a > 0.18mm standard CMOS technology, the circuit provides a 400mV voltage reference with a variation of ±0.18% from -20°C to 75°C (or less than 15ppm/°C), operates from 3.6V down to 800mV while biased with a 5nA resistor-less PTAT current source that varies ±30% over PVT, and consumes less than 20nA with an area of 0.01mm2. The same concept was used to create a temperature compensated voltage drop with regard to a monitored power supply voltage but using a 2-PMOS SCM structure with transistors of different threshold voltages. These two circuits were adopted as part of a Power Management (PM) system for RFID tag applications. The PM includes a LDO voltage regulator and a low voltage detector that require both the voltage reference and the low voltage monitor. The LDO regulated output voltage and the trip-point of the voltage detector vary +/-5.5% and +/-3.3%, respectively, over temperature, without trimming.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

Sign in / Sign up

Export Citation Format

Share Document