Trench insulated gate bipolar transistors submitted to high temperature bias stress

2005 ◽  
Vol 45 (9-11) ◽  
pp. 1728-1731 ◽  
Author(s):  
C.O. Maïga ◽  
H. Toutah ◽  
B. Tala-Ighil ◽  
B. Boudart
Keyword(s):  
High Temperature ◽  
Bipolar Transistors ◽  
Insulated Gate Bipolar Transistors ◽  
Temperature Bias ◽  
Bias Stress

Influence of High-Temperature Bias Stress on Room-Temperature VT Drift Measurements in SiC Power MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 757-762
Author(s):  
Daniel B. Habersat ◽  
Aivars Lelis ◽  
Ronald Green
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
State Of The Art ◽  
Charge Trapping ◽  
High Temperature Stress ◽  
Test Method ◽  
Power Mosfets ◽  
Temperature Bias ◽  
Bias Stress

Our results reinforce the notion of the need for an improved high-temperature gate bias (HTGB) test method — one which discourages the use of slow (greater than ~1 ms) threshold-voltage (VT) measurements at elevated temperatures and includes biased cool-down if room temperature measurements are performed, to ensure that any ephemeral effects during the high-temperature stress are observed. The paper presents a series of results on both state-of-the-art commercially-available devices as well as older vintage devices that exhibit enhanced charge-trapping effects. Although modern devices appear to be robust, it is important to ensure that any new devices released commercially, especially by new vendors, are properly evaluated for VT stability.

High temperature bias-stress-induced instability in power trench-gated MOSFETs

2014 ◽  
Vol 54 (2) ◽  
pp. 374-380 ◽  
Author(s):  
J. Hao ◽  
M. Rioux ◽  
S.A. Suliman ◽  
O.O. Awadelkarim
Keyword(s):  
High Temperature ◽  
Temperature Bias ◽  
Bias Stress

Time-Dependent Leakage Current of BaSrTiO3 Film under High Temperature Bias Stress

1998 ◽  
Vol 37 (Part 2, No. 10A) ◽  
pp. L1162-L1164 ◽  
Author(s):  
Kikuo Yamabe ◽  
Minoru Inomoto ◽  
Keitaro Imai
Keyword(s):  
High Temperature ◽  
Leakage Current ◽  
Time Dependent ◽  
Temperature Bias ◽  
Bias Stress

Demonstration of SiC Vertical Trench JFET Reliability

2012 ◽  
Vol 717-720 ◽  
pp. 1017-1020 ◽  
Author(s):  
Kevin M. Speer ◽  
Kiran Chatty ◽  
Volodymyr Bondarenko ◽  
David C. Sheridan ◽  
Kevin Matocha ◽  
...  
Keyword(s):  
High Temperature ◽  
Circuit Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Measured Parameter ◽  
System Operation ◽  
Dislocation Glide ◽  
Temperature Bias ◽  
Bias Stress

This paper demonstrates the reliability of SiC vertical trench junction field-effect transistors (VJFET). Measurements are shown which prove that the device’s intrinsic gate-source pn junction is immune to degradation associated with recombination-enhanced dislocation glide. And after subjecting VJFETs to 1,000 hours of high-temperature bias stress, no measured parameter deviated from datasheet specifications. These results reflect the maturity and reliability of SemiSouth’s SiC VJFET technology, as well as tight process control over device parameters that are critical to circuit design and long-term system operation.

Sign in / Sign up

Export Citation Format

Share Document