HREM observation of dislocations near room temperature fractures in silicon

1988 ◽  
Vol 46 ◽  
pp. 892-893
Author(s):  
M. H. Rhee ◽  
W. A. Coghlan
Keyword(s):  
Cross Section ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Dislocation Nucleation ◽  
Back Side ◽  
Ion Milling ◽  
Crystal Silicon ◽  
Flat Surfaces ◽  
Induced Fractures ◽  
Vicker’S Microhardness

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.

Silicon Carbide Die Attach Scheme for 500°C Operation

2000 ◽  
Vol 622 ◽  
Author(s):  
Liang-Yu Chen ◽  
Gary W. Hunter ◽  
Philip G. Neudeck
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Semiconductor Devices ◽  
Single Crystal Silicon ◽  
Film Material ◽  
Crystal Silicon ◽  
Pure Alumina ◽  
Die Attach

ABSTRACTSingle crystal silicon carbide (SiC) has such excellent physical, chemical, and electronic properties that SiC based semiconductor electronics can operate at temperatures in excess of 600°C well beyond the high temperature limit for Si based semiconductor devices. SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C, but only in a probe-station environment partially because suitable packaging technology for high temperature (500°C and beyond) devices is still in development. One of the core technologies necessary for high temperature electronic packaging is semiconductor die-attach with low and stable electrical resistance. This paper discusses a low resistance die-attach method and the results of testing carried out at both room temperature and 500°C in air. A 1 mm2 SiC Schottky diode die was attached to aluminum nitride (AlN) and 96% pure alumina ceramic substrates using precious metal based thick-film material. The attached test die using this scheme survived both electronically and mechanically performance and stability tests at 500°C in oxidizing environment of air for 550 hours. The upper limit of electrical resistance of the die-attach interface estimated by forward I-V curves of an attached diode before and during heat treatment indicated stable and low attach-resistance at both room-temperature and 500°C over the entire 550 hours test period. The future durability tests are also discussed.

Micro-Scale Cantilever Testing of Linear Elastic and Elastic-Plastic Materials

2012 ◽  
Vol 525-526 ◽  
pp. 57-60 ◽  
Author(s):  
J.E. Darnbrough ◽  
S. Mahalingam ◽  
Peter E.J. Flewitt
Keyword(s):  
Mechanical Properties ◽  
Single Crystal Silicon ◽  
Ion Milling ◽  
Crystal Silicon ◽  
Micro Scale ◽  
Elastic Plastic ◽  
Linear Elastic ◽  
Dual Beam ◽  
The Individual ◽  
Elastic Plastic Materials

t is increasingly a requirement to be able to determine the mechanical properties of materials: (i) at the micro-scale, (ii) that are in the form of surface coatings and (iii) that have nanoscale microstructures. As a consequence micro-scale testing is an important tool that has been developed to aid the evaluation of the mechanical properties of such materials. In this work cantilever beam specimens (typically 2μm by 2μm by 10μm in size) have been prepared by gallium ion milling and then deformed in-situ within a FEI Helios Dual Beam workstation. The latter is achieved using a force probe with a geometry suitable for loading the micro-scale test specimens. Thus force and displacement can be measured together with observing the deformation and fracture of the individual specimens. This paper considers the evaluation of the mechanical properties in particular elastic modulus, yield strength and fracture strength of materials that result in relatively large deflections to the micro-scale cantilever beams. Two materials are considered the first is linear elastic single crystal silicon and the other elastic-plastic nanocrystalline (nc) nickel. The results are discussed with respect to the reproducibility of this method of mechanical testing and the evaluated properties are compared with those derived by alternative procedures.

Formation of Buried Tisi2 Layers in Single Crystal Silicon by Ion Implantion

1987 ◽  
Vol 107 ◽  
Author(s):  
P. Madakson ◽  
G.J. Clark ◽  
F.K. Legoues ◽  
F.M. d'Heurle ◽  
J.E.E. Baglin
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Crystal Silicon ◽  
Buried Layers

Buried TiSi2 layers, about 600Å thick and 900Å below the surface, were formed in < 111> silicon by ion implantation. The implantation was done with either 120 or 170 keV Ti+ to doses ranging from 5 x 1016 to 2 x 1017 ions/cm2, and at temperatures of between ambient and 650° C. Annealing was done at 600° C, 700°C and 1000°C. Continuous buried layers were achieved only with samples implanted with doses equal or greater than 1017 ions/cm2 and at temperatures above 450°C. Below this dose TiSi2, was present only as discrete precipitates. For room temperature implants, the TiSi2, layer is formed on the surface. The damage present consists of dispersed TiSi6 precipitates and microtwins.

From the Casimir Limit to Phononic Crystals: 20 Years of Phonon Transport Studies Using Silicon-on-Insulator Technology

2013 ◽  
Vol 135 (6) ◽  
Author(s):  
Amy M. Marconnet ◽  
Mehdi Asheghi ◽  
Kenneth E. Goodson
Keyword(s):  
Room Temperature ◽  
Crystalline Silicon ◽  
Phonon Dispersion ◽  
Single Crystal Silicon ◽  
Phonon Transport ◽  
Silicon On Insulator ◽  
Boundary Scattering ◽  
Porous Films ◽  
Crystal Silicon ◽  
20 Nm

Silicon-on-insulator (SOI) technology has sparked advances in semiconductor and MEMs manufacturing and revolutionized our ability to study phonon transport phenomena by providing single-crystal silicon layers with thickness down to a few tens of nanometers. These nearly perfect crystalline silicon layers are an ideal platform for studying ballistic phonon transport and the coupling of boundary scattering with other mechanisms, including impurities and periodic pores. Early studies showed clear evidence of the size effect on thermal conduction due to phonon boundary scattering in films down to 20 nm thick and provided the first compelling room temperature evidence for the Casimir limit at room temperature. More recent studies on ultrathin films and periodically porous thin films are exploring the possibility of phonon dispersion modifications in confined geometries and porous films.

A Three-Dimensional Monte Carlo Model for Phosphorus Implants into (100) Single-Crystal Silicon

1997 ◽  
Vol 490 ◽  
Author(s):  
Myung-Sik Son ◽  
Ho-Jung Hwang
Keyword(s):  
Monte Carlo ◽  
Single Crystal ◽  
Room Temperature ◽  
Monte Carlo Model ◽  
Three Dimensional ◽  
Single Crystal Silicon ◽  
Amorphous Region ◽  
Electronic Energy ◽  
Crystal Silicon ◽  
Dynamic Simulation Model

ABSTRACTAn alternative three-dimensional (3D) Monte Carlo (MC) dynamic simulation model for phosphorus implant into (100) single-crystal silicon has been developed which incorporates the effects of channeling and damage. This model calculates the trajectories of both implanted ions and recoiled silicons and concurrently and explicitly affects both ions and recoils due to the presence of accumulative damage. In addition, the model for room-temperature implant accounts for the self-annealing effect using our defined recombination probabilities for vacancies and interstitials saved on the unit volumes. Our model has been verified by the comparison with the previously published SIMS data over commonly used energy range between 10 and 180 keV, using our proposed empirical electronic energy loss model. The 3D formations of the amorphous region and the ultra-shallow junction around the implanted region could be predicted by using our model, TRICSI (TRansport Ions into Crystal-Silicon).

Supersaturated P-Type Polycrystaline Films Produced by Rapid Thermal Annealing of High Dose Boron Ion Implants for Interconnects and Shallow Junction Diffusion Sources

1990 ◽  
Vol 182 ◽  
Author(s):  
B. Raicu ◽  
M.I. Current ◽  
W.A. Keenan ◽  
D. Mordo ◽  
R. Brennan ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Thermal Annealing ◽  
Cross Section ◽  
Rapid Thermal Annealing ◽  
Single Crystal Silicon ◽  
High Dose ◽  
Crystal Silicon ◽  
Polysilicon Films ◽  
P Type

AbstractHighly conductive p+-polysilicon films were fabricated over Si(100) and SiO2 surfaces using high-dose ion implantation and rapid thermal annealing. Resistivities close to that of single crystal silicon were achieved. These films were characterized by a variety of electrical and optical techniques as well as SIMS and cross-section TEM.

Persistent Photocurrent in InP Nanowires Heteroepitaxially Bridged Between Single Crystal Si Surfaces

2008 ◽  
Vol 1080 ◽  
Author(s):  
Ataur Sarkar ◽  
M. Saif Islam ◽  
Sungsoo Yi ◽  
A. Alec Talin
Keyword(s):  
Single Crystal ◽  
Room Temperature ◽  
Relaxation Times ◽  
Single Crystal Silicon ◽  
Surface States ◽  
Photonic Devices ◽  
Crystal Silicon ◽  
Slow Decay ◽  
Visible Laser ◽  
P Type

ABSTRACTRoom temperature photoelectrical characterization with 325-nm ultraviolet and 633-nm visible laser excitations is performed on lateral p-type InP nanowires bridged between vertically oriented heavily p-doped single crystal silicon electrodes. Experimental results under 5 V bias demonstrate persistent photoconductivity through a slow decay of excess photocurrent with relaxation times ∼110 s and ∼50 s for the UV and visible laser illuminations, respectively. Persistent photocurrent originates from the long recombination time due to carrier trapping in vacancies, defect centers, and surface states in the InP nanowires. The study opens a new understanding of trap physics of nanowire heterostructures, a critical investigation for applications of these materials in photonic devices.

Milling of Dielectric Ceramics by Fast Argon Atoms

2016 ◽  
Vol 723 ◽  
pp. 329-334
Author(s):  
Sergei Grigoriev
Keyword(s):  
Cross Section ◽  
Circular Cross Section ◽  
Ceramic Materials ◽  
Dielectric Materials ◽  
Ion Milling ◽  
Beam Source ◽  
Plasma Emitter ◽  
Flat Surfaces ◽  
Emissive Grid ◽  
Dielectric Ceramics

A new method for dielectric materials milling has been developed. Instead of well-known ion milling used for metals the dielectrics were processed by broad beams of fast argon atoms. The fast atoms were produced due to charge exchange collisions of accelerated ions. Plasma emitter of the ions was generated in hollow cathode glow discharge. Emissive grid of a circular cross-section beam source consisted of six segments. Energy of the fast atoms ranged from 1 to 3 keV. The beam source was used for production of contoured grooves on flat surfaces of hard ceramic materials. On the surface of movable seal ring made of α-corundum were produced grooves with depth of 20±0.5 μm and roughness of Ra ≈ 0.4 µm. The rate of α-corundum etching amounted to 3 μm/h.

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