From the Casimir Limit to Phononic Crystals: 20 Years of Phonon Transport Studies Using Silicon-on-Insulator Technology

2013 ◽  
Vol 135 (6) ◽  
Author(s):  
Amy M. Marconnet ◽  
Mehdi Asheghi ◽  
Kenneth E. Goodson
Keyword(s):  
Room Temperature ◽  
Crystalline Silicon ◽  
Phonon Dispersion ◽  
Single Crystal Silicon ◽  
Phonon Transport ◽  
Silicon On Insulator ◽  
Boundary Scattering ◽  
Porous Films ◽  
Crystal Silicon ◽  
20 Nm

Silicon-on-insulator (SOI) technology has sparked advances in semiconductor and MEMs manufacturing and revolutionized our ability to study phonon transport phenomena by providing single-crystal silicon layers with thickness down to a few tens of nanometers. These nearly perfect crystalline silicon layers are an ideal platform for studying ballistic phonon transport and the coupling of boundary scattering with other mechanisms, including impurities and periodic pores. Early studies showed clear evidence of the size effect on thermal conduction due to phonon boundary scattering in films down to 20 nm thick and provided the first compelling room temperature evidence for the Casimir limit at room temperature. More recent studies on ultrathin films and periodically porous thin films are exploring the possibility of phonon dispersion modifications in confined geometries and porous films.

Thermal Conductivity of Porous Silicon Layers for MEMS

1999 ◽  
Author(s):  
Uma Srinivasan ◽  
Peter Breh ◽  
Mehdi Asheghi ◽  
Maxat Touzelbaev ◽  
Kenneth E. Goodson
Keyword(s):  
Thermal Conductivity ◽  
Porous Silicon ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Boundary Scattering ◽  
Conductivity Data ◽  
Crystal Silicon ◽  
Resistance Thermometry

Abstract Porous silicon is a promising material for MEMS because of its unique electrical, thermal, optical, and absorptive properties. This work measures the thermal conductivity of a silicon layer with 40 percent porosity at temperatures between 20 and 300 K using Joule heating and electrical-resistance thermometry. The room-temperature thermal conductivity is 0.43 Wm−1K−1, which is almost three orders of magnitude less than the value for single-crystal silicon. The data are interpreted using a new model based on electron microscopy, which shows a sponge-like morphology with embedded crystalline regions. The model separately treats the contributions of the sponge-like material, in which the solid regions are assumed to be amorphous silicon, and the larger crystallites, in which the conductivity is reduced by boundary scattering. The present work is particularly useful for MEMS based on silicon with porosity below 50 percent, for which no thermal conductivity data were previously available.

Monte Carlo Simulation of In-Plane Phonon Transport in Porous Silicon Membranes

2003 ◽  
Author(s):  
David Song ◽  
Gang Chen
Keyword(s):  
Monte Carlo ◽  
Phonon Dispersion ◽  
Single Crystal Silicon ◽  
Phonon Transport ◽  
Porous Si ◽  
Crystal Silicon ◽  
Phonon Dispersion Curves ◽  
Silicon Membranes ◽  
Experimental Values ◽  
Phonon Properties

The in-plane thermal conductivity of periodic microporous single-crystal silicon membranes is simulated using a Monte Carlo method in the temperature range from 50K to 300K. The study focuses on the effect of pore boundary scattering. A gray body phonon transport is simulated, using a set of average phonon properties derived from the published experimental phonon dispersion curves. The simulation was first performed for bulk Si and the result is compared to the published experimental values. Porous Si membranes corresponding to our previous experimental configurations were then examined.

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

1998 ◽  
Vol 120 (1) ◽  
pp. 30-36 ◽  
Author(s):  
M. Asheghi ◽  
M. N. Touzelbaev ◽  
K. E. Goodson ◽  
Y. K. Leung ◽  
S. S. Wong
Keyword(s):  
Thermal Conductivity ◽  
Phonon Scattering ◽  
Single Crystal Silicon ◽  
Phonon Transport ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
A Value ◽  
Thermal Simulations ◽  
Silicon Device ◽  
Soi Substrates

Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, ds, to a value nearly 40 percent less than that of bulk silicon for ds = 0.42 μm. The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

A Simple Process for Lateral Single Crystal Silicon Nanowires

2002 ◽  
Author(s):  
Veljko Milanovic´ ◽  
Lance Doherty
Keyword(s):  
Single Crystal ◽  
Silicon Nanowires ◽  
Direct Contact ◽  
Single Crystal Silicon ◽  
Silicon On Insulator ◽  
Silicon Nanostructures ◽  
Device Layer ◽  
Crystal Silicon ◽  
Simple Process ◽  
20 Nm

In a single-mask standard photolithography based process and a single etch step, lateral silicon nanowires are fabricated according to arbitrary layout and over a range of diameters and lengths. Nanowires with diameters from ∼20 nm and with lengths ranging from 2 μm to 100 μm were fabricated in direct contact with two silicon probing pads for measurement. These nanowires are electrically isolated in the silicon-on-insulator wafer device layer, and suspended over the substrate, thereby increasing thermal and electrical isolation. Because they are formed from single crystal silicon, minimal defects are expected. The addition of a polysilicon deposition and patterning further enhances the process by allowing coaxial silicon nanostructures.

HREM observation of dislocations near room temperature fractures in silicon

1988 ◽  
Vol 46 ◽  
pp. 892-893
Author(s):  
M. H. Rhee ◽  
W. A. Coghlan
Keyword(s):  
Cross Section ◽  
Room Temperature ◽  
Single Crystal Silicon ◽  
Dislocation Nucleation ◽  
Back Side ◽  
Ion Milling ◽  
Crystal Silicon ◽  
Flat Surfaces ◽  
Induced Fractures ◽  
Vicker’S Microhardness

Silicon is believed to be an almost perfectly brittle material with cleavage occurring on {111} planes. In such a material at room temperature cleavage is expected to occur prior to any dislocation nucleation. This behavior suggests that cleavage fracture may be used to produce usable flat surfaces. Attempts to show this have failed. Such fractures produced in semiconductor silicon tend to occur on planes of variable orientation resulting in surfaces with a poor surface finish. In order to learn more about the mechanisms involved in fracture of silicon we began a HREM study of hardness indent induced fractures in thin samples of oxidized silicon.Samples of single crystal silicon were oxidized in air for 100 hours at 1000°C. Two pieces of this material were glued together and 500 μm thick cross-section samples were cut from the combined piece. The cross-section samples were indented using a Vicker's microhardness tester to produce cracks. The cracks in the samples were preserved by thinning from the back side using a combination of mechanical grinding and ion milling.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

scholarly journals A Flexible PI/Si/SiO2 Piezoresistive Microcantilever for Trace-Level Detection of Aflatoxin B1

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu
Keyword(s):  
Single Crystal ◽  
Aflatoxin B1 ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Wheatstone Bridge ◽  
Silicon On Insulator ◽  
Passivation Layer ◽  
Spring Constant ◽  
Trace Level ◽  
Crystal Silicon

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.

Silicon Carbide Die Attach Scheme for 500°C Operation

2000 ◽  
Vol 622 ◽  
Author(s):  
Liang-Yu Chen ◽  
Gary W. Hunter ◽  
Philip G. Neudeck
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Electrical Resistance ◽  
Room Temperature ◽  
Semiconductor Devices ◽  
Single Crystal Silicon ◽  
Film Material ◽  
Crystal Silicon ◽  
Pure Alumina ◽  
Die Attach

ABSTRACTSingle crystal silicon carbide (SiC) has such excellent physical, chemical, and electronic properties that SiC based semiconductor electronics can operate at temperatures in excess of 600°C well beyond the high temperature limit for Si based semiconductor devices. SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C, but only in a probe-station environment partially because suitable packaging technology for high temperature (500°C and beyond) devices is still in development. One of the core technologies necessary for high temperature electronic packaging is semiconductor die-attach with low and stable electrical resistance. This paper discusses a low resistance die-attach method and the results of testing carried out at both room temperature and 500°C in air. A 1 mm2 SiC Schottky diode die was attached to aluminum nitride (AlN) and 96% pure alumina ceramic substrates using precious metal based thick-film material. The attached test die using this scheme survived both electronically and mechanically performance and stability tests at 500°C in oxidizing environment of air for 550 hours. The upper limit of electrical resistance of the die-attach interface estimated by forward I-V curves of an attached diode before and during heat treatment indicated stable and low attach-resistance at both room-temperature and 500°C over the entire 550 hours test period. The future durability tests are also discussed.

Influence of Phonon Dispersion on Transient Thermal Response of Silicon-on-Insulator Transistors Under Self-Heating Conditions

2006 ◽  
Vol 129 (7) ◽  
pp. 790-797 ◽  
Author(s):  
Rodrigo A. Escobar ◽  
Cristina H. Amon
Keyword(s):  
Computational Models ◽  
Phonon Dispersion ◽  
Thermal Response ◽  
Domain Size ◽  
Phonon Transport ◽  
Silicon On Insulator ◽  
Nonlinear Relation ◽  
Temperature Levels ◽  
Transient Thermal ◽  
Transient Thermal Response

Lattice Boltzmann method (LBM) simulations of phonon transport are performed in one-dimensional (1D) and 2D computational models of a silicon-on-insulator transistor, in order to investigate its transient thermal response under Joule heating conditions, which cause a nonequilibrium region of high temperature known as a hotspot. Predictions from Fourier diffusion are compared to those from a gray LBM based on the Debye assumption, and from a dispersion LBM which incorporates nonlinear dispersion for all phonon branches, including explicit treatment of optical phonons without simplifying assumptions. The simulations cover the effects of hotspot size and heat pulse duration, considering a frequency-dependent heat source term. Results indicate that, for both models, a transition from a Fourier diffusion regime to a ballistic phonon transport regime occurs as the hotspot size is decreased to tens of nanometers. The transition is characterized by the appearance of boundary effects, as well as by the propagation of thermal energy in the form of multiple, superimposed phonon waves. Additionally, hotspot peak temperature levels predicted by the dispersion LBM are found to be higher than those from Fourier diffusion predictions, displaying a nonlinear relation to hotspot size, for a given, fixed, domain size.

scholarly journals Анодное окисление слоев кремний-на-изоляторе, созданных методом водородного переноса

2019 ◽  
Vol 53 (2) ◽  
pp. 253
Author(s):  
И.Е. Тысченко ◽  
И.В. Попов ◽  
Е.В. Спесивцев
Keyword(s):  
Oxidation Rate ◽  
Hydrogen Transfer ◽  
Single Crystal Silicon ◽  
Interatomic Interaction ◽  
Surface Region ◽  
Bound State ◽  
Silicon On Insulator ◽  
Bulk Single Crystal ◽  
Crystal Silicon ◽  
Insulator Layer

AbstractThe anodic oxidation rate of silicon-on-insulator films fabricated by hydrogen transfer is studied as a function of the temperature of subsequent annealing. It is established that the oxidation rate of transferred silicon-on-insulator films is five times lower compared to the oxidation rate of bulk single-crystal silicon samples. The oxidation rate increases, as the annealing temperature is elevated in the range 700–1100°C and as the depth of gradually removed anode-oxidized layers is increased. The results obtained in the study are attributed to an increase in the efficiencies of the anodic current and oxygen–silicon interatomic interaction due to the annealing of defects and due to release of hydrogen from the bound state, respectively. The formation of hydrogen bubbles in the surface region of silicon due to the diffusion of hydrogen, released in the process of the oxidation reaction, towards micropores in the silicon-on-insulator layer is detected.

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