Microstructures of Al(Pd, Nb) and Al(Ti) lines for VLSI
Very Large Scale Integration necessitated an ongoing and rapid decrease in the minimum feature size which must be made on silicon devices with the aims of improving productivity and performance. Conductor lines are commonly made from Al(Cu). Widths of 1.5 μm for conductor lines are common today, submicron lines are in late stages of development and 0.25 μm lines will be needed. These dimensions present new issues since the feature size is of the same order as the grain size of the Al and other metal alloys presently used for chip wiring. In order to make on-chip wiring reliable at these dimensions it is necessary to optimise the resistance to the stresses placed on them: electromigration due to increasing current densities; thermal stresses due to differences in thermal expansivities. The kinetics of both processes are dominated by interface transport. The resistance of the metal to both stresses can be modified by alloying.