Stability of nanocrystalline silicon bottom-gate thin film transistors with silicon nitride gate dielectric

We report on the fabrication of dual-gate pentacene organic thin-film transistors (OTFTs) using a plasma-enhanced atomic layer deposited (PEALD) 150 nm thick Al2O3 as a bottom gate dielectric and a 300 nm thick parylene or a PEALD 200 nm thick Al2O3 as both a top gate dielectric and a passivation layer. The threshold voltage (Vth) of OTFT with a 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with a PEALD 200 nm thick Al2O3 as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of Vth of OTFT with the dual-gate structure has been successfully understood by an analysis of electrostatic potential.

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Monolithically Integrated p- & n- Channel Thin Film Transistors of Nanocrystalline Silicon on Plastic Substrates

MRS Proceedings ◽

10.1557/proc-808-a4.6 ◽

2004 ◽

Vol 808 ◽

Cited By ~ 3

Author(s):

I-Chun Cheng ◽

Sigurd Wagner

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Structural Evolution ◽

Nanocrystalline Silicon ◽

Leakage Currents ◽

Plastic Substrates ◽

Monolithically Integrated ◽

Glass Substrates ◽

Electron Field

ABSTRACTInverters made of monolithically integrated p- and n-channel thin film transistors of nanocrystalline silicon were demonstrated on both Corning 1737 glass and Kapton E polyimide substrates. The TFT's geometry is staggered top-gate, bottom-source/rain. A nc-Si:H seed layer promotes the structural evolution of the nc-Si:H channel. Electron field-effect mobilities of 15 - 30 cm2V−1s-1 and hole mobilities of 0.15 - 0.35 cm2V−1s−1 were obtained. Slightly lower carrier mobilities were observed in the TFTs made on polyimide than on glass substrates. High gate leakage currents and offsets between the supply HIGH voltages and the output voltages in the inverters indicate that the low-temperature gate dielectric needs improvement.

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The Characterization of Bottom-gate Thin Film Transistors adapted Nanocrystalline Silicon as Active Layer by Catalytic CVD at Low Temperature

ECS Transactions ◽

10.1149/1.3204414 ◽

2019 ◽

Vol 25 (3) ◽

pp. 259-262

Author(s):

Youn-Jin Lee ◽

Kyoung-Min Lee ◽

Jae-Dam Hwang ◽

Kil-Sun No ◽

Kap Soo Yoon ◽

...

Keyword(s):

Thin Film ◽

Low Temperature ◽

Active Layer ◽

Thin Film Transistors ◽

Nanocrystalline Silicon ◽

Bottom Gate ◽

Catalytic Cvd

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Reliability of Silicon Nitride Gate Dielectric in Vertical Thin-Film Transistors

MRS Proceedings ◽

10.1557/proc-0989-a08-05 ◽

2007 ◽

Vol 989 ◽

Cited By ~ 2

Author(s):

Maryam Moradi ◽

D. Striakhilev ◽

I. Chan ◽

A. Nathan ◽

N. I. Cho ◽

...

Keyword(s):

Thin Film ◽

Silicon Nitride ◽

Leakage Current ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Electrical Breakdown ◽

Thick Films ◽

Experimental Result ◽

Process Conditions ◽

Vertical Sidewall

AbstractIn this work, we have conducted a systematic investigation of leakage current and electrical breakdown of plasma enhanced chemical vapor deposited (PECVD) silicon nitride, both for planar films and deposited films on the vertical sidewall for the application of the vertical thin film transistors. The thickness evolution of physical properties and electrical characteristics of silicon nitride films in the range of 50 to 300 nm are investigated. Electrical breakdown strength for 150-300nm thick films was approximately 7 MV/cm, whereas the value dropped to ~3MV/cm for 50nm thick films deposited under the same process conditions. It is shown that the early failure of the thin nitride is accompanied by the increase of the pinholes number. For the vertical thin film transistors, the experimental result shows the reliability and leakage current of the gate dielectric depends on the step coverage of the silicon nitride film on the vertical sidewall.

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