VLSI design techniques for low power MAC unit: A review

2021 ◽  
Author(s):  
Ajay Kumar Sahu ◽  
Rashmi Samanth ◽  
Tanya Mendez ◽  
Subramanya G. Nayak ◽  
K. Vishnumurthy Kedlaya
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Design Techniques

Low Power VLSI Design Techniques - The Current State

1998 ◽  
Vol 5 (2) ◽  
pp. 153-176
Author(s):  
Jo Dale Carothers ◽  
Radjakichenin Radjassamy
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Current State ◽  
Low Power Vlsi Design ◽  
Design Techniques

VLSI design of spread spectrum encoding low power RFID tag baseband processor

2009 ◽  
Author(s):  
Zhu Qiuling ◽  
Zhang Chun ◽  
Wang Xiaohui ◽  
Wang Ziqiang ◽  
Li fule ◽  
...  
Keyword(s):  
Low Power ◽  
Spread Spectrum ◽  
Vlsi Design ◽  
Rfid Tag ◽  
Baseband Processor

Low-Power VLSI Design: An Overview

1995 ◽  
pp. 1-12
Author(s):  
Abdellatif Bellaouar ◽  
Mohamed I. Elmasry
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Low Power Vlsi Design

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

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