Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

The Evaluation of Electric Power by Separate Analysis of Fourier Transform Components

This paper presents a substantiation of an approach for the evaluation of components of apparent power and intended to simplify the computational procedures which usually should be implemented in order to process the preliminary sampled waveform of instantaneous power. The results of carried out studies have shown that both active and reactive power can be calculated by the analysis of calculated components of sine and cosine Fourier transforms. This paper also presents the discussion of restrictions, which should be imposed on the duration of the analyzed signal and on frequencies of the auxiliary trigonometric functions, which are applied in order to calculate components of Fourier transform which are used for the evaluation of active and reactive power. The compliance with these restrictions allows us to eliminate the undesirable bias of active and reactive power estimation caused by the refusal from the decomposition of the analyzed waveform of the instantaneous power by applying the complete system of orthogonal trigonometric functions, as the evaluation of components of the apparent power is attained based on separate analysis of sine and cosine Fourier transforms calculated for the analyzed signal. The results of carried out simulations illustrate the frequency dependencies of sine Fourier transform calculated for the case of compliance with the restrictions, which allow to attain the highest accuracy of estimation and for the case when the duration of analyzed signal does not fit these restrictions.

Error Performance of Subsampling Digital Power Estimation for Integrated Receivers

Estimation of signal power levels at the output of integrated receiver building blocks is a vital function as the block voltage or power gains are set based on sensed power levels to maintain constant levels at block outputs in the receiver chain. RF and IF level real-time gain settings are determined with Automatic Gain Control (AGC) loops. AGC loop circuit topologies are usually based on analog detection circuits. These analog power detection circuits are based on techniques such as envelope detection, and logarithmic amplification usually accompanied by severe accuracy issues such as Process, Voltage and Temperature (PVT) spreads preventing correct gain adjustments. Adopting a dominantly digital approach to detect the signal power would ensure a significant reduction in PVT spreads. This work presents a review of the subsampling digital power estimation to create low power digital power estimations alternative to analog methods. The simulations of the method are applied to an AM and a 64-QAM signal. Simulation results show that the power estimation error is within the acceptable level of [Formula: see text][Formula: see text]dB.

Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique

Nowadays, high-end Field-Programmable Gate Arrays (FPGAs) are capable of implementing relatively high-performance systems in the field of Digital Signal Processing (DSP). Due to the abundant application of multipliers, their implementation efficiency and performance have become a critical issue in designing the DSP systems. On the other hand, FPGAs consume a large amount of power due to their complex circuitry. So, the power estimation of FPGA implementations at an early design stage has become a critical design metric. Various models are available in the literature based on Look-up Tables (LUTs), but not much literature is available on speed-optimized multiplier design using DSP slices only. In this paper, an embedded multiplier (12.0 IP core) has been analyzed and customized for different Input/Output (I/O) configurations to estimate the power using Vivado Design Suite (2014.4) targeted to the Zynq-family FPGA device (Zynq evolution and development kit). The embedded multiplier IP has been optimized for performance using two different approaches, i.e., Mults (DSP)-based and LUTs-based. Post-synthesis attributes have been used for formulating the power estimation models based on Artificial Neural Network (ANN) and curve fitting and regression technique. The power values estimated from the proposed models have been authenticated with reference to those assessed from the commercial tool. Based on the results obtained, ANN-based model provides average errors of 0.73% and 0.88% for the LUTs and DSP-based designs, respectively. Whereas, the model based on curve fitting and regression technique provides average errors of 3.61% and 1.59% for the LUTs and DSP-based designs, respectively. The timing analysis has been done to get the design performance and time complexity of the proposed models. Area analysis of the design has also been performed in order to report the resource utilization.