Semiconductor Device Failures in Power Converter Service Conditions

EPE Journal ◽  
1998 ◽  
Vol 7 (3-4) ◽  
pp. 12-17 ◽  
Author(s):  
Stefan Januszewski ◽  
Maria Kociszewska-Szczerbik ◽  
Henryk Swiaiek ◽  
Grzegorz Swiatek
Keyword(s):  
Semiconductor Device ◽  
Power Converter ◽  
Service Conditions

Investigation of Active Power Cycling Combined With Passive Thermal Cycles on Discrete Power Electronic Devices

2019 ◽  
Vol 141 (3) ◽  
Author(s):  
Alexander Otto ◽  
Sven Rzepka ◽  
Bernhard Wunderle
Keyword(s):  
System Integration ◽  
Semiconductor Device ◽  
Reliability Assessment ◽  
Active Power ◽  
Testing Time ◽  
Automotive Electronics ◽  
Thermal Cycles ◽  
System Architectures ◽  
Power Cycling ◽  
Service Conditions

Active power cycling (APC) is a standardized and well-established method for reliability assessment and product qualification in power electronics (PEs) technologies. Repetitive pulses of load current are applied to cause cyclic thermal swings in the p–n junction and in the whole semiconductor device. They induce thermo-mechanical stresses, which ultimately leads to the typical interconnect failure in the “devices under test.” However, these tests are insensitive with respect to new automotive system architectures, in which PEs devices are exposed to additional loads besides the intrinsic thermal swings. The trends in PEs toward miniaturization, higher power density, heterogeneous system integration, and the deployment of PEs in harsher environments combined with longer lifetime and higher uptime requirements strongly increase the reliability demands in general and the need for more improved reliability assessment methodologies in particular. The new testing methods shall be more comprehensive and more efficient, i.e., they shall simultaneously cover the real service conditions better and reduce testing time. One promising approach is the combination of loading factors—such as the superposition of active power cycling by passive thermal cycles (TC). Both loading factors are well known to cause most relevant failure mechanisms in PEs. In reality, the PE devices are exposed to both factors simultaneously. Hence, this load case should also be replicated in the test. The paper will report a systematic investigation of such superimposed test schemes, which cover the case of self-heating and passive heating (from neighboring elements) of the PEs devices under real service conditions. Typical discrete PEs components in TO-200 packages are selected as test vehicles as they are likewise relevant for the domains of consumer or automotive electronics. The paper details the test concept and discusses the quantitative and qualitative test results.

Defects in β-SiC thin films grown on α-SiC substrates

1988 ◽  
Vol 46 ◽  
pp. 568-569
Author(s):  
Karren L. More
Keyword(s):  
Thin Films ◽  
Semiconductor Device ◽  
Lattice Mismatch ◽  
Chemical Vapor ◽  
Substrate Material ◽  
Growth Interface ◽  
Si Substrates ◽  
Thermal Expansion Coefficients ◽  
Device Applications ◽  
Expansion Coefficients

Beta-SiC is an ideal candidate material for use in semiconductor device applications. Currently, monocrystalline β-SiC thin films are epitaxially grown on {100} Si substrates by chemical vapor deposition (CVD). These films, however, contain a high density of defects such as stacking faults, microtwins, and antiphase boundaries (APBs) as a result of the 20% lattice mismatch across the growth interface and an 8% difference in thermal expansion coefficients between Si and SiC. An ideal substrate material for the growth of β-SiC is α-SiC. Unfortunately, high purity, bulk α-SiC single crystals are very difficult to grow. The major source of SiC suitable for use as a substrate material is the random growth of {0001} 6H α-SiC crystals in an Acheson furnace used to make SiC grit for abrasive applications. To prepare clean, atomically smooth surfaces, the substrates are oxidized at 1473 K in flowing 02 for 1.5 h which removes ∽50 nm of the as-grown surface. The natural {0001} surface can terminate as either a Si (0001) layer or as a C (0001) layer.

Applications of SIMS to electronic materials and devices

1992 ◽  
Vol 50 (2) ◽  
pp. 1682-1683
Author(s):  
S.F. Corcoran
Keyword(s):  
Depth Distribution ◽  
Secondary Ion Mass Spectrometry ◽  
Semiconductor Device ◽  
Electronic Materials ◽  
Profile Analysis ◽  
Semiconductor Industry ◽  
Small Diameter ◽  
Depth Resolution ◽  
Detection Sensitivity

Over the past decade secondary ion mass spectrometry (SIMS) has played an increasingly important role in the characterization of electronic materials and devices. The ability of SIMS to provide part per million detection sensitivity for most elements while maintaining excellent depth resolution has made this technique indispensable in the semiconductor industry. Today SIMS is used extensively in the characterization of dopant profiles, thin film analysis, and trace analysis in bulk materials. The SIMS technique also lends itself to 2-D and 3-D imaging via either the use of stigmatic ion optics or small diameter primary beams.By far the most common application of SIMS is the determination of the depth distribution of dopants (B, As, P) intentionally introduced into semiconductor materials via ion implantation or epitaxial growth. Such measurements are critical since the dopant concentration and depth distribution can seriously affect the performance of a semiconductor device. In a typical depth profile analysis, keV ion sputtering is used to remove successive layers the sample.

Structural and electronic properties of defects in semiconductors

1995 ◽  
Vol 53 ◽  
pp. 4-5
Author(s):  
J.L. Batstone
Keyword(s):  
Semiconductor Device ◽  
Chemical Vapor ◽  
Misfit Strain ◽  
Organic Chemical ◽  
Extended Defects ◽  
Transmission Electron ◽  
Semiconductor Thin Films ◽  
Wide Range ◽  
Metal Organic ◽  
Film Substrate

The development of growth techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy during the last fifteen years has resulted in the growth of high quality epitaxial semiconductor thin films for the semiconductor device industry. The III-V and II-VI semiconductors exhibit a wide range of fundamental band gap energies, enabling the fabrication of sophisticated optoelectronic devices such as lasers and electroluminescent displays. However, the radiative efficiency of such devices is strongly affected by the presence of optically and electrically active defects within the epitaxial layer; thus an understanding of factors influencing the defect densities is required.Extended defects such as dislocations, twins, stacking faults and grain boundaries can occur during epitaxial growth to relieve the misfit strain that builds up. Such defects can nucleate either at surfaces or thin film/substrate interfaces and the growth and nucleation events can be determined by in situ transmission electron microscopy (TEM).

Metal Microstructures in Advanced CMOS Devices

1996 ◽  
Vol 54 ◽  
pp. 358-359
Author(s):  
L. M. Gignac ◽  
K. P. Rodbell
Keyword(s):  
Grain Boundaries ◽  
Semiconductor Device ◽  
Chemical Vapor ◽  
Microstructural Characterization ◽  
Metal Films ◽  
Thin Metal ◽  
Electrical Performance ◽  
Thin Metal Films ◽  
Chemical Vapor Deposited ◽  
Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

Bestimmung des zerebralen Blutflusses mittels des 81 Rb/81 mKr-Generatorsystems

1990 ◽  
Vol 29 (01) ◽  
pp. 7-12 ◽  
Author(s):  
J. Bialy ◽  
F.-J. Hans ◽  
E. Oberhausen ◽  
W.J. Peters ◽  
M. Schmitt ◽  
...  
Keyword(s):  
Blood Flow ◽  
Cerebral Blood Flow ◽  
Blood Circulation ◽  
Semiconductor Device ◽  
Animal Experiments ◽  
Initial Value ◽  
Brain Arteries ◽  
Sufficient Concentration ◽  
Static Quantity

A method is being developed which not only measures cerebral blood flow as a static quantity but also its changes with time. For that purpose a semiconductor device ascertains the proportion of intracerebral81 Rb and 81mKr activities. By opening the haemato-encephalic barrier in animal experiments a sufficient concentration of intracerebral81 Rb could be attained and the modified blood circulation after step-wise ligature of all brain arteries brought into relation to the corresponding Rb/Kr quotient. Over the range from undisturbed to completely interrupted cerebral blood flow this quotient varied up to 25% of its initial value.

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