Program/erase injection current characteristics of a low-voltage low-power NROM using high-K materials as the tunnel dielectric

2006 ◽  
Vol 21 (4) ◽  
pp. 507-512 ◽  
Author(s):  
Yimao Cai ◽  
Ru Huang ◽  
Xiaonan Shan ◽  
Yan Li ◽  
Falong Zhou ◽  
...  
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Injection Current ◽  
High K ◽  
Current Characteristics ◽  
High K Materials

Low voltage and low power embedded 2T-SONOS flash memories improved by using P-type devices and high-K materials

2005 ◽  
Vol 49 (11) ◽  
pp. 1849-1856 ◽  
Author(s):  
R. van Schaijk ◽  
M. Slotboom ◽  
M. van Duuren ◽  
D. Dormans ◽  
N. Akil ◽  
...  
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Flash Memories ◽  
High K ◽  
High K Materials ◽  
P Type

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

2013 ◽  
Vol 100 (6) ◽  
pp. 803-817 ◽  
Author(s):  
D. Nirmal ◽  
P. Vijayakumar ◽  
P. Patrick Chella Samuel ◽  
Binola K. Jebalin ◽  
N. Mohankumar
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
High K ◽  
High K Materials ◽  
Power Application

Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT

Nanoscale ◽  
2015 ◽  
Vol 7 (19) ◽  
pp. 8695-8700 ◽  
Author(s):  
Changjian Zhou ◽  
Xinsheng Wang ◽  
Salahuddin Raju ◽  
Ziyuan Lin ◽  
Daniel Villaroman ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Power Device ◽  
Enhancement Mode ◽  
High K ◽  
High K Gate Dielectric

Ultra high-k dielectric enables low-voltage enhancement-mode MoS2 transistor with high ON/OFF ratio, leading to low-power device.

Nanocrystals in High-k Dielectric Stacks for Non-Volatile Memory Applications

2006 ◽  
Vol 51 ◽  
pp. 156-166 ◽  
Author(s):  
Marco Fanciulli ◽  
Michele Perego ◽  
Caroline Bonafos ◽  
A. Mouti ◽  
S. Schamm ◽  
...  
Keyword(s):  
Leakage Current ◽  
Retention Time ◽  
Flash Memory ◽  
Low Voltage ◽  
Memory Device ◽  
Research Strategies ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Materials

The possibility to use semiconducting or metallic nanocrystals (ncs) embedded in a SiO2 matrix as charge storage elements in novel non volatile memory devices has been widely explored in the last ten years. The replacement of the continuous polysilicon layer of a conventional flash memory device by a 2-dimensional nanoparticle array presents several advantages but the fundamental trade-off between programming and data retention characteristics has not been overcome yet. The main problem is the limited retention time basically due to charge loss by leakage current through the ultra-thin SiO2 tunnelling dielectric. A longer retention time can be achieved by increasing the tunnel oxide thickness. This however implies higher operating voltages and consequently a reduced write/erase speed. Using high-k materials for tunnel and/or gate oxide it is in principle possible to achieve the goal of a low voltage non volatile memory device. The high dielectric constant of these materials allows using thicker tunnel oxide reducing leakage current. Several approaches have been explored to synthesise ordered arrays of ncs in SiO2 but the transfer of these methodologies to the synthesis of 2-d array of ncs in high-k materials is not trivial. In this work we address the material science issues related to the synthesis of metallic and semiconducting ncs in high-k materials using different techniques. A detailed review of the state of the art in the field is presented and further research strategies are suggested.

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals Low-voltage activated (LVA) inward current in murine antral smooth muscle cells is an artifact

2021 ◽  
Author(s):  
Ji Yeon Lee ◽  
Haifeng Zheng ◽  
Kenton M. Sanders ◽  
Sang Don Koh
Keyword(s):  
Low Voltage ◽  
External Solution ◽  
Physiological Salt Solution ◽  
Channel Blockers ◽  
Free Solution ◽  
Inward Current ◽  
High K ◽  
Voltage Dependent ◽  
Inward Currents ◽  
Rich Solution

We characterized the two types of voltage-dependent inward currents in murine antral SMC. The HVA and LVA inward currents were identified when cells were bathed in Ca2+-containing physiological salt solution. We examined whether the LVA inward current was due to: 1) T-type Ca2+ channels, 2) Ca2+-activated Cl- channels, 3) non-selective cation channels (NSCC) or 4) voltage-dependent K+ channels with internal Cs+-rich solution. Replacement of external Ca2+ (2 mM) with equimolar Ba2+ increased the amplitude of the HVA current but blocked the LVA current. Nicardipine blocked the HVA current, and in the presence of nicardipine, T-type Ca2+ blockers failed to block LVA. The Cl- channel antagonist had little effect on LVA. Cation-free external solution completely abolished both HVA and LVA. Addition of Ca2+ in cation-free solution restored only HVA currents. Addition of K+ (5 mM) to cation-free solution induced LVA current that reversed at -20 mV. These data suggest that LVA is not due to T-type Ca2+ channels, Ca2+-activated Cl- channels or NSCC. Antral SMC express A-type K+ currents (KA) and delayed rectifying K+ currents (KV) with dialysis of high K+ (140 mM) solution. When cells were exposed to high K+ external solution with dialysis of Cs+-rich solution in the presence of nicardipine, LVA was evoked and reversed at positive potentials. These HK-induced inward currents were blocked by K+ channel blockers, 4-aminopyridine and TEA. In conclusion, LVA inward currents can be generated by K+ influx via KA and KV channels in murine antral SMC when cells were dialyzed with Cs+-rich solution.

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

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