Reconfigurable nonvolatile boolean logic with one-transistor-two-memristor for in-memory computing

Author(s):  
Ziling Wang ◽  
Li Luo ◽  
Jie Li ◽  
Lidan Wang ◽  
shukai duan

Abstract In-memory computing is highly expected to break the von Neumann bottleneck and memory wall. Memristor with inherent nonvolatile property is considered to be a strong candidate to execute this new computing paradigm. In this work, we have presented a reconfigurable nonvolatile logic method based on one-transistor-two-memristor (1T2M) device structure, inhibiting the sneak path in the large-scale crossbar array. By merely adjusting the applied voltage signals, all 16 binary Boolean logic functions can be achieved in a single cell. More complex computing tasks including one-bit parallel full adder and Set-Reset latch have also been realized with optimization, showing simple operation process, high flexibility, and low computational complexity. The circuit verification based on cadence PSpice simulation is also provided, proving the feasibility of the proposed design. The work in this paper is intended to make progress in constructing architectures for in-memory computing paradigm.

Author(s):  
James A. Anderson

Brains and computers were twins separated at birth. In 1943, it was known that action potentials were all or none, approximating TRUE or FALSE. In that year, Walter Pitts and Warren McCulloch wrote a paper suggesting that neurons were computing logic functions and that networks of such neurons could compute any finite logic function. This was a bold and exciting large-scale theory of brain function. Around the same time, the first digital computer, the ENIAC, was being built. The McCulloch-Pitts work was well known to the scientists building ENIAC. The connection between them appeared explicitly in a report by John von Neumann on the successor to the ENIAC, the EDVAC. It soon became clear that biological brain computation was not based on logic functions. However, this idea was believed by many scientists for decades. A brilliant wrong theory can sometimes cause trouble.


2014 ◽  
Vol 24 (04) ◽  
pp. 1442004
Author(s):  
Ichitaro Yamazaki ◽  
Jakub Kurzak ◽  
Piotr Luszczek ◽  
Jack Dongarra

A systolic array provides an alternative computing paradigm to the von Neumann architecture. Though its hardware implementation has failed as a paradigm to design integrated circuits in the past, we are now discovering that the systolic array as a software virtualization layer can lead to an extremely scalable execution paradigm. To demonstrate this scalability, in this paper, we design and implement a 3D virtual systolic array to compute a tile QR decomposition of a tall-and-skinny dense matrix. Our implementation is based on a state-of-the-art algorithm that factorizes a panel based on a tree-reduction. Freed from the constraint of a planar layout, we present a three-dimensional virtual systolic array architecture for this algorithm. Using a runtime developed as a part of the Parallel Ultra Light Systolic Array Runtime (PULSAR) project, we demonstrate on a Cray-XT5 machine how our virtual systolic array can be mapped to a large-scale machine and obtain excellent parallel performance. This is an important contribution since such a QR decomposition is used, for example, to compute a least squares solution of an overdetermined system, which arises in many scientific and engineering problems.


Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 496 ◽  
Author(s):  
John Reuben

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory R E A D operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory R E A D and W R I T E operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than I M P L Y , N A N D , N O R and other similar logic primitives.


2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Tao Yue ◽  
Da Zhao ◽  
Duc T. T. Phan ◽  
Xiaolin Wang ◽  
Joshua Jonghyun Park ◽  
...  

AbstractThe vascular network of the circulatory system plays a vital role in maintaining homeostasis in the human body. In this paper, a novel modular microfluidic system with a vertical two-layered configuration is developed to generate large-scale perfused microvascular networks in vitro. The two-layer polydimethylsiloxane (PDMS) configuration allows the tissue chambers and medium channels not only to be designed and fabricated independently but also to be aligned and bonded accordingly. This method can produce a modular microfluidic system that has high flexibility and scalability to design an integrated platform with multiple perfused vascularized tissues with high densities. The medium channel was designed with a rhombic shape and fabricated to be semiclosed to form a capillary burst valve in the vertical direction, serving as the interface between the medium channels and tissue chambers. Angiogenesis and anastomosis at the vertical interface were successfully achieved by using different combinations of tissue chambers and medium channels. Various large-scale microvascular networks were generated and quantified in terms of vessel length and density. Minimal leakage of the perfused 70-kDa FITC-dextran confirmed the lumenization of the microvascular networks and the formation of tight vertical interconnections between the microvascular networks and medium channels in different structural layers. This platform enables the culturing of interconnected, large-scale perfused vascularized tissue networks with high density and scalability for a wide range of multiorgan-on-a-chip applications, including basic biological studies and drug screening.


2018 ◽  
Vol 8 (4) ◽  
pp. 34 ◽  
Author(s):  
Vishal Saxena ◽  
Xinyu Wu ◽  
Ira Srivastava ◽  
Kehan Zhu

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.


2017 ◽  
Vol 139 (30) ◽  
pp. 10176-10179 ◽  
Author(s):  
Xiangmeng Qu ◽  
Shaopeng Wang ◽  
Zhilei Ge ◽  
Jianbang Wang ◽  
Guangbao Yao ◽  
...  

Complexity ◽  
2017 ◽  
Vol 2017 ◽  
pp. 1-12
Author(s):  
Vedhas Pandit ◽  
Björn Schuller

We present a new technique for defining, analysing, and simplifying digital functions, through hand-calculations, easily demonstrable therefore in the classrooms. It can be extended to represent discrete systems beyond the Boolean logic. The method is graphical in nature and provides complete ‘‘implementation-free” description of the logical functions, similar to binary decision diagrams (BDDs) and Karnaugh-maps (K-maps). Transforming a function into the proposed representations (also the inverse) is a very intuitive process, easy enough that a person can hand-calculate these transformations. The algorithmic nature allows for its computing-based implementations. Because the proposed technique effectively transforms a function into a scatter plot, it is possible to represent multiple functions simultaneously. Usability of the method, therefore, is constrained neither by the number of inputs of the function nor by its outputs in theory. This, being a new paradigm, offers a lot of scope for further research. Here, we put forward a few of the strategies invented so far for using the proposed representation for simplifying the logic functions. Finally, we present extensions of the method: one that extends its applicability to multivalued discrete systems beyond Boolean functions and the other that represents the variants in terms of the coordinate system in use.


2017 ◽  
Vol 7 (3) ◽  
pp. 27
Author(s):  
Kyle B Davidson ◽  
Bahram Asiabanpour ◽  
Zaid Almusaied

The shortage of freshwater resources in the world has developed the need for sustainable, cost-effective technologies that can produce freshwater on a large scale. Current solutions often have extensive manufacturing requirements, or involve the use of large quantities of energy or toxic chemicals. Atmospheric water generating solutions that minimize the depletion of natural resources can be achieved by incorporating biomimetics, a classification of design inspired by nature. This research seeks to optimize thermoelectric cooling systems for use in water harvesting applications by analyzing the different factors that affect surface temperature and water condensation in TEC devices. Further experiments will be directed towards developing a robust, repeatable system, as well as an accurate measurement system. Surface modifications, device structure and orientation, and power generation will also be studied to better understand the ideal conditions for maximum water collection in thermoelectric cooling systems.


1995 ◽  
Vol 396 ◽  
Author(s):  
Shu Qin ◽  
James D. Bernstein ◽  
Chung Chan

AbstractHydrogen etching effects in plasma ion implantation (PII) doping processes alter device structure and implant dopant profile and reduce the retained implant dose. This has particular relevance to the shallow junction devices of ultra large scale integrated circuits (ULSI). Hydrogen etching of semiconductor materials including Si, poly-Si, SiO2, Al, and photoresist films have been investigated. The effects of varying different PII process parameters are presented. The experimental data show that the spontaneous etching by hydrogen radicals enhanced by ion bombardment is responsible for the etching phenomena. A computer simulation is used to predict the as-implanted impurity profile and the retained implant dose for a shallow junction doping when the etching effect is considered.


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