Impact of nearby lightning on photovoltaic modules converters

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Sami Barmada ◽  
Alessandro Formisano ◽  
Jesus C. Hernandez ◽  
Francisco José J. Sánchez Sutil ◽  
Carlo Petrarca
Keyword(s):  
Field Effect Transistors ◽  
Buck Converter ◽  
Oxide Semiconductor ◽  
Electromagnetic Transients ◽  
Lightning Strike ◽  
Pv System ◽  
Content Type ◽  
Power Switch ◽  
Protection Systems ◽  
Converter Topology

Purpose The lightning phenomenon is one of the main threats in photovoltaic (PV) applications. Suitable protection systems avoid major damages from direct strikes but also nearby strikes may induce overvoltage transients in the module itself and in the power conditioning circuitry, which can permanently damage the system. The effects on the PV system sensibly depend on the converter topology and on the adopted power switch. In the present study, a comparative analysis of the transient response due to a nearby lightning strike (LS) is carried out for three PV systems, each equipped with a different converter, namely, boost, buck and buck–boost, based on either silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFET) or insulated gate bipolar transistors controlled power switch devices, allowing in this way an analysis at different switching frequencies. The purpose of this paper is to present the results of the numerical analysis to help the design of suited protection systems. Design/methodology/approach Using a recently introduced three-dimensional semi-analytical method to simulate the electromagnetic transients caused in PV modules by nearby LSs, we investigate numerically the effect of a LS on the electronic circuits connecting the module to the alternate current (AC) power systems. This study adopts numerical simulations because experimental analyses are not easy to perform and does not grant a sufficient coverage of all statistically relevant aspects. The approach was validated in a previous paper against available experimental data. Findings It is found that the load voltage is not severely interested by the strike effects, thanks to the low pass filters present at the converter output, whereas a relatively high overvoltage develops between the negative pin of the inner circuitry and the “ground” voltage reference. The overcurrent present in the active switches is hardly comparable because of the different topologies and working frequencies; however, the highest overcurrent is observed in the buck converter topology, with SiC MOSFET technology, although it shows the fastest decay. Originality/value This research proposes, to the best of the authors’ knowledge, a comprehensive comparison of the indirect lighting strike effects on the converter connected to PV panels. A proper design of the lightning and surge protection system should take into account such aspects to reduce the risk of induced overvoltage and overcurrent transients.

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Abhay Sanjay Vidhyadharan ◽  
Sanjay Vidhyadharan
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Low Voltage ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Schmitt Trigger ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Requirement ◽  
Content Type

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

scholarly journals High Gain and Reduced Switch Stress DC-DC Converter Topology for PV System

2018 ◽  
Vol 7 (04) ◽  
pp. 23808-23816
Author(s):  
C. Srideepa ◽  
S.Sathish Kumar ◽  
R. Nagarajan
Keyword(s):  
High Gain ◽  
Photovoltaic System ◽  
Voltage Gain ◽  
Pv System ◽  
Power Switch ◽  
High Voltage Gain ◽  
Voltage Stress ◽  
Converter Topology ◽  
State Resistance ◽  
Two Hybrid

This paper presents a new high step-up isolated DC-DC converter topology for photovoltaic system. The suggested configuration provides a converter with high voltage gain and reduced switch stress by using three coupled inductor with two hybrid voltage multiplier cell. The operation of the proposed converter is based on a charging capacitor with a single switch in its structure. A passive clamp circuit composed of capacitors and diodes is employed in the converter structure for lowering the voltage stress on the power switch as well as increasing the voltage gain of the converter. Since the voltage stress is low in the provided topology, a switch with a small ON-state resistance can be used. As a result, the losses are decreased and the efficiency is increased. The design of DC-DC boost converter is also discussed in detail. Simulation of DC-DC converter is performed in MATLAB/Simulink and the result are verified

Comparison of low cost, insulated aluminium substrates used as integrated heat sinks with conventional technology

2009 ◽  
Vol 26 (2) ◽  
pp. 3-9 ◽  
Author(s):  
E. Eisermann ◽  
K. Höll ◽  
W. Smetana ◽  
W. Tusler ◽  
M. Unger ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Point Of View ◽  
Heat Sinks ◽  
Oxide Semiconductor ◽  
Content Type ◽  
Light Emitting ◽  
Conventional Technology ◽  
High Intensity Light

PurposeThe purpose of this paper is to describe two new thick film paste systems (one glass‐based and the other polymer‐based) for insulating aluminium substrates and allowing components like high‐intensity light‐emitting diodes to be attached to a conductor deposited on the dielectric.Design/methodology/approachComparative measurements of the thermal resistance of different substrates mounted with metal‐oxide semiconductor field‐effect transistors were made.FindingsThe thermal advantages of these two technologies have been proved.Originality/valueThis paper presents useful comparative data from a replicated application using different combinations of substrates. The paper shows how the superior properties of the two new systems have been proven by thermal resistance measurements. From a thermal point of view, it is only the expensive 4 W m−1 K−1 insulated metal substrate that competes with the “low cost” systems.

TEM study of Cosi2 formation via annealing of Co-Ti bilayers on Si

1995 ◽  
Vol 53 ◽  
pp. 464-465
Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier
Keyword(s):  
Thermal Instability ◽  
Lattice Mismatch ◽  
Field Effect Transistors ◽  
Contact Layer ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Surface Layers ◽  
Silicide Layer ◽  
Small Lattice ◽  
Buried Layers

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Analysis and Design of a Multi-Port DC-DC Converter for Interfacing PV Systems

Energies ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 1943
Author(s):  
Bader N. Alajmi ◽  
Mostafa I. Marei ◽  
Ibrahim Abdelsalam ◽  
Mohamed F. AlHajri
Keyword(s):  
High Frequency ◽  
Computer Aided Design ◽  
Electromagnetic Transients ◽  
Pv System ◽  
Analysis And Design ◽  
Pv Systems ◽  
Point Tracking ◽  
Power Point Tracking ◽  
Power Point ◽  
Aided Design

A high-frequency multi-port (HFMP) direct current (DC) to DC converter is presented. The proposed HFMP is utilized to interface a photovoltaic (PV) system. The presented HFMP is compact and can perform maximum power point tracking. It consists of a high-frequency transformer with many identical input windings and one output winding. Each input winding is connected to a PV module through an H-bridge inverter, and the maximum PV power is tracked using the perturb and observe (P&O) technique. The output winding is connected to a DC bus through a rectifier. The detailed analysis and operation of the proposed HFMP DC-DC converter are presented. Extensive numerical simulations are conducted, using power system computer aided design (PSCAD)/electromagnetic transients including DC (EMTDC) software, to evaluate the operation and dynamic behavior of the proposed PV interfacing scheme. In addition, an experimental setup is built to verify the performance of the HFMP DC-DC converter.

scholarly journals Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 441
Author(s):  
Marcello Cioni ◽  
Alessandro Bertacchini ◽  
Alessandro Mucci ◽  
Nicolò Zagni ◽  
Giovanni Verzellesi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Driving Voltage ◽  
Drain Voltage ◽  
Current Increase ◽  
Mode Operation ◽  
Switch Mode ◽  
Gate Signal ◽  
A Current ◽  
Parameter Monitoring

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

scholarly journals Computation of Energy Absorption and Residual Voltage in a Fourth Rail LRT Station Arresters in EMTP-RV: A Comparative Study

2021 ◽  
Author(s):  
Farah Asyikin Abd Rahman ◽  
Mohd Zainal Abidin Ab Kadir ◽  
Ungku Anisa Ungku Amirulddin ◽  
Miszaina Osman
Keyword(s):  
Electromagnetic Transients ◽  
Lightning Strike ◽  
Voltage Gradient ◽  
Urban Transit ◽  
Residual Voltage ◽  
Voltage Ratio ◽  
Lightning Channel ◽  
Breakdown Region ◽  
Current Region ◽  
Performance Results

AbstractThis paper presents a study on the performance of a fourth rail direct current (DC) urban transit affected by an indirect lightning strike. The indirect lightning strike was replicated and represented by a lightning-induced overvoltage by means of the Rusck model, with the sum of two Heidler functions as its lightning channel base current input, on a perfect conducting ground. This study aims to determine whether an indirect lightning strike has any influence with regard to the performance of the LRT Kelana Jaya line, a fourth rail DC urban transit station arrester. The simulations were carried out using the Electromagnetic Transients Program–Restructured Version (EMTP–RV), which includes the comparison performance results between the 3EB4-010 arrester and PDTA09 arrester when induced by a 90 kA (9/200 µs). The results demonstrated that the PDTA09 arrester showed better coordination with the insulated rail bracket of the fourth rail. It allowed a lower residual voltage and a more dynamic response, eventually resulting in better voltage gradient in the pre-breakdown region and decreased residual voltage ratio in the high current region.

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