TEM study of Cosi2 formation via annealing of Co-Ti bilayers on Si

1995 ◽  
Vol 53 ◽  
pp. 464-465
Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier
Keyword(s):  
Thermal Instability ◽  
Lattice Mismatch ◽  
Field Effect Transistors ◽  
Contact Layer ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Surface Layers ◽  
Silicide Layer ◽  
Small Lattice ◽  
Buried Layers

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.

Self-Assembly CoSi2-Nanostructures for Fabrication of Schottky Barrier MOSFETs on SOI

2001 ◽  
Vol 686 ◽  
Author(s):  
Patrick Kluth ◽  
Qing-Tai Zhao ◽  
Stephan Winnerl ◽  
Siegfried Mantl
Keyword(s):  
Schottky Barrier ◽  
Self Assembly ◽  
Strain Field ◽  
Field Effect Transistors ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Silicide Layer ◽  
20 Nm ◽  
Soi Substrates ◽  
Substrate Doping

AbstractA new self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 70 nm gate-length Schottky barrier metal oxide semiconductor field effect transistors (SBMOSFETs) on silicon-on-insulator (SOI) substrates. This technique involves only conventional optical lithography and standard silicon processing steps. It is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal processing. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. Single-crystalline CoSi2 layers grown by molecular beam allotaxy (MBA) on thin SOI substrates were patterned using this technique. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. During the RTON-step a 6 nm thin SiO2 is formed on top of the gap which is used as a gate oxide. The SBMOSFETs can be driven as both p-channel and n-channel devices without complementary substrate doping and show good I-V characteristics.

Simultaneous Formation of n- and p-Type Ohmic Contacts to 4H-SiC Using the Binary Ni/Al System

2008 ◽  
Vol 1069 ◽  
Author(s):  
Kazuhiro Ito ◽  
Toshitake Onishi ◽  
Hidehisa Takeda ◽  
Susumu Tsukimoto ◽  
Mitsuru Konno ◽  
...  
Keyword(s):  
Layer Thickness ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
High Vacuum ◽  
Contact Layer ◽  
Ultra High Vacuum ◽  
Oxide Semiconductor ◽  
Simultaneous Formation ◽  
Ohmic Behavior ◽  
P Type

ABSTRACTFabrication procedure for silicon carbide power metal oxide semiconductor field effect transistors can be improved through simultaneous formation of ohmic contacts on both the n-source and p-well regions. We have succeeded in the simultaneous formation of Ni/Al ohmic contacts to n- and p-type SiC after annealing at 1000°C for 5 mins in an ultra-high vacuum. Ohmic contacts to n-type SiC were found when Al-layer thickness was less than about 5 nm while ohmic contacts to p-type SiC were observed for an Al-layer thickness greater than about 5 nm. Only the contacts with Al-layer thicknesses in the range of 5 to 6 nm exhibited ohmic behavior to both n- and p-type SiC, with specific contact resistances of 1.8 × 10−4 Ωcm2 and 1.2 × 10−2 Ωcm2 for n- and p-type SiC, respectively. An about 100 nm-thick contact layer was uniformly formed on the SiC substrate and polycrystalline δ-Ni2Si(Al) grains were formed at the contact/SiC interface. The distribution in values for the Al/Ni ratio in the δ-Ni2Si(Al) grains which exhibited ohmic behavior to both n- and p-type SiC was the largest. The smallest average δ-Ni2Si(Al) grain size was also observed in these contacts. Thus, the large distribution in the Al/Ni ratios and a fine microstructure were found to be characteristic of the ohmic contacts to both n- and p-type SiC.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 441
Author(s):  
Marcello Cioni ◽  
Alessandro Bertacchini ◽  
Alessandro Mucci ◽  
Nicolò Zagni ◽  
Giovanni Verzellesi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Driving Voltage ◽  
Drain Voltage ◽  
Current Increase ◽  
Mode Operation ◽  
Switch Mode ◽  
Gate Signal ◽  
A Current ◽  
Parameter Monitoring

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

scholarly journals Atomic Layer Deposition (ALD) of Metal Gates for CMOS

2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang
Keyword(s):  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Material Selection ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
Metal Gates ◽  
Layer Deposition

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

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