scholarly journals Test Architecture for Systolic Array of Edge-based AI Accelerator

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Umair Saeed Solangi ◽  
Muhammad Ibtesam ◽  
Muhammad Adil Ansari ◽  
Jinuk Kim ◽  
Sungju Park
Keyword(s):  
Systolic Array ◽  
Edge Based ◽  
Test Architecture

Bi-way sorter. a two-dimensional systolic array

1992 ◽  
Vol 139 (2) ◽  
pp. 147
Author(s):  
G.A. Orton ◽  
L.E. Peppard ◽  
S.G. Akl
Keyword(s):  
Systolic Array ◽  
Two Dimensional

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

scholarly journals Enabling Internet of Media Things With Edge-Based Virtual Multimedia Sensors

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 59255-59269
Author(s):  
Anselmo Luiz Eden Battisti ◽  
Debora Christina Muchaluat-Saade ◽  
Flavia C. Delicato
Keyword(s):  
Edge Based
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