Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs

2021 ◽  
Author(s):  
Yunchuan Wang ◽  
Li Zhang ◽  
Fengyi Mei ◽  
Yongzhen Chen ◽  
Jiangfeng Wu
Keyword(s):  
Digital Calibration ◽  
Capacitor Mismatch ◽  
Gain Error

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

A New Switched-Capacitor Multiply-by-Two Amplifier with Reduced Mismatch Sensitivity

2011 ◽  
Vol 403-408 ◽  
pp. 1224-1227
Author(s):  
Chi Chang Lu
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
High Resolution ◽  
Power Efficiency ◽  
New Technique ◽  
Switched Capacitor ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Simulation Results

A new switched-capacitor multiply-by-two amplifier with an accurate gain of two is presented. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. Monte-Carlo simulation results are presented to confirm the feasibility of this new technique, demonstrating its suitability for high-resolution pipelined A/D converter.

A design method of capacitor arrays for high-resolution SAR ADCs

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 249-255
Author(s):  
Yuqing Wu ◽  
Jizhong Shen ◽  
Jun Liang ◽  
Maoqun Yao
Keyword(s):  
High Resolution ◽  
Design Method ◽  
Design Flow ◽  
Content Type ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Multi Stage ◽  
Gain Error ◽  
Capacitance Effects ◽  
Capacitor Arrays

Purpose The design method of high-resolution capacitor arrays was proposed to improve the precision of successive approximation register (SAR) analog-to-digital converters (ADCs) without calibration and optimize the circuit area. Design/methodology/approach According to calculation of equivalent series capacitors and change of voltage at the comparator input node, two three-stage structures of capacitor arrays and a general design flow of the multi-stage capacitor arrays were presented. Non-ideal factors on the capacitor arrays were analyzed, and the applications of the two structures were explained based on the capacitor mismatch. Findings A multi-stage capacitor array for 16-bit SAR ADCs was implemented. The simulation result shows that its nonlinear error was less than 0.3LSB with no gain error and the sampling capacitance accounted for 92.42% of the total capacitance. Effects of capacitive parasitic and mismatch on capacitor arrays were confirmed. Originality/value The proposed method focused on capacitor arrays design of high-resolution SAR ADCs. It effectively reduced nonlinear errors, improved SNR and optimized the area of SAR ADCs. The design method was suitable for SAR ADCs with different resolutions to improve their precision.

An 8-bit 5-Gsample/s Time-Interleaved Analog-to-Digital Converter Used for Optical Communication

2013 ◽  
Vol 756-759 ◽  
pp. 205-208
Author(s):  
Yu Han Gao ◽  
Yong Lu Wang ◽  
Guang Bin Chen ◽  
Zheng Ping Zhang ◽  
Can Zhu ◽  
...  
Keyword(s):  
Digital Calibration ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Gain Error ◽  
Sige Bicmos ◽  
Low Jitter ◽  
Bicmos Process ◽  
Time Interleaved ◽  
Sample Time

In this paper, we present an 8-bit 5 Gsample/s time-interleaved analog-to-digital converter (TI ADC). A 4-phase low jitter clock is designed to control four 1.25 Gsample/s sub-ADCs which is implemented using folding and interpolating architecture. Digital calibration is used to adjust the offset error and gain error of sub-ADCs. Meanwhile, serial peripheral interface (SPI) is adopted to adjust mismatch of gain and sample time between sub-ADCs. The whole TI ADC is designed using a 0.18m SiGe BiCMOS process. The whole ADC has a SNR of about 45 dB at the input frequency of 495 MHZ and an equivalent ENOB of 7.2 bits.

A 7.21-bit ENOB 100MS/s 1.51mW Inverter based Pipelined ADC with Digital Calibration for Breast Cancer Detection System

2020 ◽  
Vol 140 (6) ◽  
pp. 585-591
Author(s):  
Yoshihiro Masui ◽  
Tsukasa Nishimiya ◽  
Allex Uemi ◽  
Akihiro Toya ◽  
Takamaro Kikkawa
Keyword(s):  
Breast Cancer ◽  
Cancer Detection ◽  
Detection System ◽  
Breast Cancer Detection ◽  
Digital Calibration ◽  
Pipelined Adc
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