A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

2007 ◽  
Author(s):  
I-Chyn Wey ◽  
You-Gang Chen ◽  
Changhong Yu ◽  
Jie Chen ◽  
An-Yeu Wu
Keyword(s):  
Circuit Design ◽  
Noise Immunity ◽  
Design And Implementation ◽  
Noise Tolerant

Design and Implementation of a High Accuracy Interpolation Encoder IC for Magnetic Sensor

2019 ◽  
Author(s):  
Wen-Yu Chen ◽  
Yi-Feng Zhang ◽  
Paul C.-P. Chao ◽  
Eka Fitrah Pribadi
Keyword(s):  
Measurement System ◽  
Noise Immunity ◽  
Supply Voltage ◽  
High Accuracy ◽  
Cmos Process ◽  
Specific Method ◽  
Clock Frequency ◽  
Design And Implementation ◽  
Equal Distance ◽  
Interpolation Technique

Abstract The magnetic encoder (ME) always employs sensor passing through periodic and equal distance grating and then generates periodic quadrature scaling signals for displacement measurement. The phase is relative to the movement. To improve encoder accuracy or resolution, electronic interpolation technique had been developed to subdivide the phase of quadrature scaling signals. According to the trends, this paper proposed a specific method with excellent noise immunity characteristic and a complete calibration process to improve the accuracy of the system. The designed circuit is taped-out using TSMC 0.18-μm CMOS process, where the active area is 1643 μm × 1676 μm. The chip has the specification of 3.3 V supply voltage, 20 MHz clock frequency, and 0.0859 mW power consumption. The accuracy of the measurement system is 1.065um.

Circuit Design and Implementation for a Class of Hysteretic Systems

2013 ◽  
Vol 313-314 ◽  
pp. 312-315
Author(s):  
Cun Zhi Pan ◽  
Ya Qian Liu ◽  
Jin Juan Xue
Keyword(s):  
Circuit Design ◽  
Circuit Theory ◽  
Circuit Board ◽  
Hysteresis Curve ◽  
Hysteretic Model ◽  
Hysteretic Systems ◽  
Design And Implementation ◽  
Data Acquisition Card ◽  
Signal Output ◽  
Simulation Results

Bouc-Wen model is a kind of more representative differential hysteretic model, which has the advantages of strong universality and parameters easily identification and that can better approximate the hysteresis curve. By using nonlinear system dynamics circuit theory, Bouc-Wen mathematical model is transformed into circuit model, the simulation results test the validity of the designed circuit and a physical circuit board is finally made. An experimental setup is established with the data acquisition card and related software. Circuit debugging and signal output under typical excitation of the circuit board are performed, the results show that the circuit board is be feasible to demonstrate the Bouc-Wen model.

scholarly journals Long Channel Keeper Based Open Loop Difference Amplifier Domino For Noise Tolerant Low Power Or Gates

2019 ◽  
Vol 8 (10) ◽  
pp. 3331-3340
Keyword(s):  
Power Consumption ◽  
Noise Immunity ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Open Loop ◽  
High Input ◽  
Noise Tolerant ◽  
Capacitive Loading ◽  
Long Channel ◽  
Or Gate

This paper proposes an open loop difference amplifier with long channel keeper technique for domino logic circuits implemented as wide fan in OR gate. Currently OR gates suffer from high capacitive loading and delays due to such loading. The proposed design uses single stage of comparison and dual keeper arrangement to generate and hold the output logic state. This technique effectively reduces the high input loading from capacitance and manages the power consumption by switching based on the generated difference voltage. As compared to standard footerless domino SFLD, the proposed design OLDA has shown to reduce power consumption by 42% in 64 bit configuration. It has increased average noise immunity by 2.03 times, while maintaining same speed as compared to SFLD. All simulations are done in CMOS technology with 90nm PTM LP models

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