Distributed Genetic Algorithm of Test Generation For Digital Circuits

2006 ◽  
Author(s):  
Y.A. Skobtsov ◽  
A.i. El-Khatib ◽  
D.E. Ivanov
Keyword(s):  
Genetic Algorithm ◽  
Test Generation ◽  
Digital Circuits ◽  
Distributed Genetic Algorithm

Test Generation for Glitch Faults of Crosstalk Effects in Digital Circuits Based on Genetic Algorithm with Niche

2010 ◽  
Vol 20-23 ◽  
pp. 647-652
Author(s):  
Zhong Liang Pan ◽  
Ling Chen
Keyword(s):  
Genetic Algorithm ◽  
Test Generation ◽  
Digital Circuits ◽  
Signal Integrity ◽  
Test Method ◽  
Coupling Effects ◽  
Vector Generation ◽  
Signal Path ◽  
Test Vectors ◽  
Test Vector Generation

The more signal path ways close to each other in digital circuits, the greater the coupling effects. The coupling effects can led to an increasing number of signal integrity related faults such as crosstalk faults. In this paper, the glitch faults of crosstalk effects are studied. First of all, the test vector generation using signal paths of circuits is given. Secondly, a new test method for crosstalk faults in digital circuits is presented, which is based on the genetic algorithm with niche. The test method can detect the maximal crosstalk effects, i.e. the test vectors to be produced is to switch a set of aggressors that maximizes the switching of total coupling effects. The test method is also used to produce the test vectors of multiple crosstalk faults. The experimental results show that the method proposed in this paper can get the test vectors of the multiple crosstalk faults if the faults are testable.

scholarly journals Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli
Keyword(s):  
Temporal Logic ◽  
Test Generation ◽  
Digital Circuits ◽  
Difficult Problem ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Temporal Behavior ◽  
Generation Algorithm

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.

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